David Wu 615514c16d rockchip: clk: Add rk3368 SARADC clock support ... The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>		2017-10-01 00:33:30 +02:00
..
asm	rockchip: clk: Add rk3368 SARADC clock support	2017-10-01 00:33:30 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00