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d494cdb97e
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
602 lines
14 KiB
Text
602 lines
14 KiB
Text
/*
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* Gazerbeam CON Device Tree Source
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*
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* (C) Copyright 2015
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include "gdsys/mpc8308.dtsi"
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/include/ "gdsys/gazerbeam-base.dtsi"
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/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi"
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/include/ "gdsys/soc/i2c/dallas-rtc.dtsi"
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/include/ "gdsys/soc/lbc/gazerbeam.dtsi"
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/include/ "gdsys/soc/nor/flash-80k-partition.dtsi"
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&board_lbc {
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FPGA0:iocon_uart@1,0 {
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reg = <0x1 0x0 0x100000>;
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little-endian;
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interrupts = <48 0x8>;
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interrupt-parent = <&ipic>;
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};
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FPGA1:iocon_uart@2,0 {
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reg = <0x2 0x0 0x100000>;
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little-endian;
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interrupts = <17 0x8>;
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interrupt-parent = <&ipic>;
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};
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};
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&FPGA0 {
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compatible = "gdsys,iocon_fpga";
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#gpio-cells = <2>;
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gpio-controller;
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bus = <&FPGA0BUS>;
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unit_id = <0>;
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fpga-type = <1>;
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usb_base = <0x0080>;
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audio_base = <0x0040>;
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timebase_base = <0x013c>;
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/*
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* for every interrupt source there must be a dataset specifying
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* 1. type (1: standard)
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* 2. status register offset
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* 3. mask register offset
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* 4. default mask
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*/
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fpga_interrupt_sources =
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<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
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<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
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/*
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* for every interrupt there must be a dataset specifying
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* 1. type (1: status, 2: event)
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* 2. interrupt source index
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* 3. interrupt register bit
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* 4. mask register bit
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*/
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#fpga_interrupt_map-cells = <4>;
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fpga_interrupt_map =
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<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
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<1 0 0 0>, /* 1: VIDEO 0 */
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<1 0 1 1>, /* 2: VIDEO 1 */
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<1 0 2 2>, /* 3: VIDEO IC 0 */
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<1 0 3 3>, /* 4: VIDEO IC 1 */
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<1 0 4 4>, /* 5: IIC MAIN */
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<1 0 6 6>, /* 6: IIC VIDEO 0 */
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<1 0 7 7>, /* 7: IIC VIDEO 1 */
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<1 1 0 0>, /* 8: OSD 0 */
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<1 1 1 1>, /* 9: OSD 1 */
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<1 1 2 2>, /* 10: SPDIF 0 */
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<1 1 3 3>, /* 11: SPDIF 1 */
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<1 0 12 12>, /* 12: COMM 0 */
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<1 0 13 13>, /* 13: COMM 1 */
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<1 0 10 10>, /* 14: COMM 2 */
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<1 0 11 11>, /* 15: COMM 3 */
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<2 0 5 5>, /* 16: MDIO */
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<1 0 8 8>, /* 17: PHY */
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<1 1 4 4>, /* 18: RS232 */
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<1 1 5 5>, /* 19: AUDIO */
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<1 1 8 8>, /* 20: PROC_AUDIO */
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<1 1 7 7>, /* 21: USB/ETH-UART INT */
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<2 1 10 10>, /* 22: AXI Bridge 0 */
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<2 1 11 11>, /* 23: AXI Bridge 1 */
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<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
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<>;
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};
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&FPGA1 {
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compatible = "gdsys,iocon_fpga";
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#gpio-cells = <2>;
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gpio-controller;
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bus = <&FPGA1BUS>;
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unit_id = <1>;
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fpga-type = <1>;
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usb_base = <0x0070>;
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audio_base = <0x0040>;
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timebase_base = <0x013c>;
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/*
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* for every interrupt source there must be a dataset specifying
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* 1. type (1: standard)
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* 2. status register offset
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* 3. mask register offset
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* 4. default mask
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*/
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fpga_interrupt_sources =
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<1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */
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<1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */
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/*
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* for every interrupt there must be a dataset specifying
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* 1. type (1: status, 2: event)
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* 2. interrupt source index
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* 3. interrupt register bit
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* 4. mask register bit
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*/
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#fpga_interrupt_map-cells = <4>;
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fpga_interrupt_map =
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<1 0 14 14>, /* 0: EXTENDED_INTERRUPT */
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<1 0 0 0>, /* 1: VIDEO 0 */
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<1 0 1 1>, /* 2: VIDEO 1 */
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<1 0 2 2>, /* 3: VIDEO IC 0 */
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<1 0 3 3>, /* 4: VIDEO IC 1 */
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<1 0 4 4>, /* 5: IIC MAIN */
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<1 0 6 6>, /* 6: IIC VIDEO 0 */
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<1 0 7 7>, /* 7: IIC VIDEO 1 */
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<1 1 0 0>, /* 8: OSD 0 */
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<1 1 1 1>, /* 9: OSD 1 */
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<1 1 2 2>, /* 10: SPDIF 0 */
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<1 1 3 3>, /* 11: SPDIF 1 */
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<1 0 12 12>, /* 12: COMM 0 */
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<1 0 13 13>, /* 13: COMM 1 */
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<1 0 10 10>, /* 14: COMM 2 */
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<1 0 11 11>, /* 15: COMM 3 */
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<2 0 5 5>, /* 16: MDIO */
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<1 0 8 8>, /* 17: PHY */
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<1 1 4 4>, /* 18: RS232 */
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<1 1 5 5>, /* 19: AUDIO */
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<1 1 8 8>, /* 20: PROC_AUDIO */
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<1 1 7 7>, /* 21: USB/ETH-UART INT */
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<2 1 10 10>, /* 22: AXI Bridge 0 */
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<2 1 11 11>, /* 23: AXI Bridge 1 */
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<2 1 9 9>, /* 24: USB/ETH-Secondary IIC */
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<>;
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};
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/ {
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FPGA0BUS: fpga0bus {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x00002000>;
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compatible = "gdsys,soc";
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fpga0_rs232 {
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compatible = "gdsys,ihs_trans_rs232";
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reg = <0x50 0x08>;
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little-endian;
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};
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fpga0_uart_usb {
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compatible = "gdsys,ihs_simple_uart";
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reg = <0xa0 0x08>;
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little-endian;
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fpga_interrupts = <21>;
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line = <0>;
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};
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fpga0_iic_main {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x60 0x10>;
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little-endian;
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fpga_interrupts = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga0_dp_video0_redriver: fpga0_dp_video0_redriver {
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compatible = "ti,sn75dp130";
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reg = <0x2c>;
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eq-i2c-enable = <3 2 1 0
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3 2 1 0
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
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};
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fpga0_dp_video1_redriver: fpga0_dp_video1_redriver {
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compatible = "ti,sn75dp130";
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reg = <0x2e>;
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eq-i2c-enable = <3 2 1 0
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3 2 1 0
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
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};
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lm77@48 {
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compatible = "national,lm77";
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reg = <0x48>;
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};
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ads1015@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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};
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ads1015@4b {
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compatible = "ti,ads1015";
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reg = <0x4b>;
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};
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};
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fpga0_video0 {
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compatible = "gdsys,ihs_video_out";
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reg = <0x100 0x40>;
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little-endian;
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fpga_interrupts = <1 8>; /* VIDEO OSD */
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osd_base = <0x180>;
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osd_buffer_base = <0x1000>;
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spdif_audio_base = <0x1e0>;
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video_index = <0>;
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video_id = <0>;
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fpga-force-pos-pol;
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sync-source;
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fpga-pb-pixels = <2730>; /* 8192 / 3 */
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fpga-ra-lines = <2>;
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video_tx = <&fpga0_dp_video0>;
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clk_gen = <&fpga0_video0_clkgen>;
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ddc_ci = <&fpga0_dp_video0>;
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};
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fpga0_iic_video0 {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x1c0 0x10>;
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little-endian;
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fpga_interrupts = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga0_video0_clkgen: fpga0_video0_clkgen {
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compatible = "idt,ics8n3qv01";
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reg = <0x6e>;
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channel = <0>;
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};
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};
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fpga0_axi_video0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "gdsys,ihs_axi";
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reg = <0x170 0x10>;
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little-endian;
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fpga_interrupts = <22>;
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fpga0_dp_video0: fpga0_dp_video0 {
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compatible = "gdsys,logicore_dp_tx";
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reg = <0x44a10000 0x1000>;
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little-endian;
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redriver = <&fpga0_dp_video0_redriver>;
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video_id = <0>;
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};
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};
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fpga0_video1 {
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compatible = "gdsys,ihs_video_out";
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reg = <0x200 0x40>;
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little-endian;
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fpga_interrupts = <2 9>; /* VIDEO OSD */
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osd_base = <0x280>;
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osd_buffer_base = <0x2000>;
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spdif_audio_base = <0x2e0>;
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video_index = <1>;
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video_id = <1>;
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fpga-force-pos-pol;
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sync-source;
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fpga-pb-pixels = <2730>; /* 8192 / 3 */
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fpga-ra-lines = <2>;
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video_tx = <&fpga0_dp_video1>;
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clk_gen = <&fpga0_video1_clkgen>;
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ddc_ci = <&fpga0_dp_video1>;
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};
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fpga0_iic_video1 {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x2c0 0x10>;
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little-endian;
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fpga_interrupts = <7>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga0_video1_clkgen: fpga0_video1_clkgen {
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compatible = "idt,ics8n3qv01";
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reg = <0x6e>;
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channel = <1>;
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};
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};
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fpga0_axi_video1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "gdsys,ihs_axi";
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reg = <0x270 0x10>;
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little-endian;
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fpga_interrupts = <23>;
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fpga0_dp_video1: fpga0_dp_video1 {
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compatible = "gdsys,logicore_dp_tx";
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reg = <0x44a10000 0x1000>;
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little-endian;
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redriver = <&fpga0_dp_video1_redriver>;
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video_id = <1>;
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};
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};
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fpga0_iic_usb {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0xb0 0x10>;
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little-endian;
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fpga_interrupts = <24>;
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#address-cells = <1>;
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#size-cells = <0>;
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pca9555@20 {
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compatible = "nxp,pca9555";
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reg = <0x20>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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fpga0_ep0 {
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compatible = "gdsys,io-endpoint";
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reg = < 0x020 0x10
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0x320 0x10
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0x340 0x10
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0x360 0x10>;
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little-endian;
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irq-model-local;
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fpga_interrupts = <12 13 14 15>;
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pollcycle = <200>;
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nprot_channel = <16>;
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uart_line = <0>;
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ep_index = <0>;
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line_protocol = <1>;
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};
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fpga0_mdio {
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compatible = "gdsys,ihs_mdiomaster";
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reg = <0x0058 0x10>;
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little-endian;
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fpga_interrupts = <16>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga0_phy0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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device_type ="ethernet-phy";
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reg = <0>;
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};
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fpga0_phy1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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device_type ="ethernet-phy";
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reg = <1>;
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};
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fpga0_phy2 {
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compatible = "ethernet-phy-ieee802.3-c45";
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device_type ="ethernet-phy";
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reg = <2>;
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};
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fpga0_phy3 {
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compatible = "ethernet-phy-ieee802.3-c45";
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device_type ="ethernet-phy";
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reg = <3>;
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};
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};
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};
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FPGA1BUS: fpga1bus {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x00002000>;
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compatible = "gdsys,soc";
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fpga1_uart_usb {
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compatible = "gdsys,ihs_simple_uart";
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reg = <0xa0 0x08>;
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little-endian;
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fpga_interrupts = <21>;
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line = <4>; /* TODO check and FIX */
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};
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fpga1_iic_main {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x60 0x10>;
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little-endian;
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fpga_interrupts = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga1_dp_video0_redriver: fpga1_dp_video0_redriver {
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compatible = "ti,sn75dp130";
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reg = <0x2c>;
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eq-i2c-enable = <3 2 1 0
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3 2 1 0
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
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};
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fpga1_dp_video1_redriver: fpga1_dp_video1_redriver {
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compatible = "ti,sn75dp130";
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reg = <0x2e>;
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eq-i2c-enable = <3 2 1 0
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3 2 1 0
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3 2 1 0
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3 2 1 0>; /* 3.5 dB for all pe values for all lanes */
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};
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lm77@48 {
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compatible = "national,lm77";
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reg = <0x48>;
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};
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ads1015@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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};
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ads1015@4b {
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compatible = "ti,ads1015";
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reg = <0x4b>;
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};
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};
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fpga1_video0 {
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compatible = "gdsys,ihs_video_out";
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reg = <0x100 0x40>;
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little-endian;
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fpga_interrupts = <1 8>; /* VIDEO OSD */
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osd_base = <0x180>;
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osd_buffer_base = <0x1000>;
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spdif_audio_base = <0x1e0>;
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video_index = <0>;
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video_id = <4>;
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fpga-force-pos-pol;
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sync-source;
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fpga-pb-pixels = <2730>; /* 8192 / 3 */
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fpga-ra-lines = <2>;
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video_tx = <&fpga1_dp_video0>;
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clk_gen = <&fpga1_video0_clkgen>;
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ddc_ci = <&fpga1_dp_video0>;
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};
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fpga1_iic_video0 {
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compatible = "gdsys,ihs_i2cmaster";
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reg = <0x1c0 0x10>;
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little-endian;
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fpga_interrupts = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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fpga1_video0_clkgen: fpga1_video0_clkgen {
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compatible = "idt,ics8n3qv01";
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reg = <0x6e>;
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channel = <4>;
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};
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};
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fpga1_axi_video0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "gdsys,ihs_axi";
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reg = <0x170 0x10>;
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little-endian;
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fpga_interrupts = <22>;
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fpga1_dp_video0: fpga1_dp_video0 {
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compatible = "gdsys,logicore_dp_tx";
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reg = <0x44a10000 0x1000>;
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little-endian;
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redriver = <&fpga1_dp_video0_redriver>;
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video_id = <4>;
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};
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};
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fpga1_video1 {
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compatible = "gdsys,ihs_video_out";
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reg = <0x200 0x40>;
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little-endian;
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fpga_interrupts = <2 9>; /* VIDEO OSD */
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osd_base = <0x280>;
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osd_buffer_base = <0x2000>;
|
|
spdif_audio_base = <0x2e0>;
|
|
video_index = <1>;
|
|
video_id = <5>;
|
|
fpga-force-pos-pol;
|
|
sync-source;
|
|
fpga-pb-pixels = <2730>; /* 8192 / 3 */
|
|
fpga-ra-lines = <2>;
|
|
video_tx = <&fpga1_dp_video1>;
|
|
clk_gen = <&fpga1_video1_clkgen>;
|
|
ddc_ci = <&fpga1_dp_video1>;
|
|
};
|
|
|
|
fpga1_iic_video1 {
|
|
compatible = "gdsys,ihs_i2cmaster";
|
|
reg = <0x2c0 0x10>;
|
|
little-endian;
|
|
fpga_interrupts = <7>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fpga1_video1_clkgen: fpga1_video1_clkgen {
|
|
compatible = "idt,ics8n3qv01";
|
|
reg = <0x6e>;
|
|
channel = <5>;
|
|
};
|
|
};
|
|
|
|
fpga1_axi_video1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "gdsys,ihs_axi";
|
|
reg = <0x270 0x10>;
|
|
little-endian;
|
|
fpga_interrupts = <23>;
|
|
|
|
fpga1_dp_video1: fpga1_dp_video1 {
|
|
compatible = "gdsys,logicore_dp_tx";
|
|
reg = <0x44a10000 0x1000>;
|
|
little-endian;
|
|
redriver = <&fpga1_dp_video1_redriver>;
|
|
video_id = <5>;
|
|
};
|
|
};
|
|
|
|
fpga1_iic_usb {
|
|
compatible = "gdsys,ihs_i2cmaster";
|
|
reg = <0xb0 0x10>;
|
|
little-endian;
|
|
fpga_interrupts = <24>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pca9555@20 {
|
|
compatible = "nxp,pca9555";
|
|
reg = <0x20>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
};
|
|
};
|
|
|
|
fpga1_ep0 {
|
|
compatible = "gdsys,io-endpoint";
|
|
reg = < 0x020 0x10
|
|
0x320 0x10
|
|
0x340 0x10
|
|
0x360 0x10>;
|
|
little-endian;
|
|
irq-model-local;
|
|
fpga_interrupts = <12 13 14 15>;
|
|
pollcycle = <200>;
|
|
nprot_channel = <17>;
|
|
uart_line = <1>;
|
|
ep_index = <0>;
|
|
line_protocol = <1>;
|
|
};
|
|
|
|
fpga1_mdio {
|
|
compatible = "gdsys,ihs_mdiomaster";
|
|
reg = <0x0058 0x10>;
|
|
little-endian;
|
|
fpga_interrupts = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fpga1_phy0 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
device_type ="ethernet-phy";
|
|
reg = <0>;
|
|
};
|
|
fpga1_phy1 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
device_type ="ethernet-phy";
|
|
reg = <1>;
|
|
};
|
|
fpga1_phy2 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
device_type ="ethernet-phy";
|
|
reg = <2>;
|
|
};
|
|
fpga1_phy3 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
device_type ="ethernet-phy";
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
#include "gdsys/gazerbeam-uboot.dtsi"
|