mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
601 lines
15 KiB
C
601 lines
15 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Basic U-Boot I2C interface for STn8500/DB8500
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* Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Only 7-bit I2C device addresses are supported.
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*/
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#include <common.h>
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#include <i2c.h>
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#include "u8500_i2c.h"
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */
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#define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */
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#define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */
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#define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */
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#define TX_FIFO_THRESHOLD 0x4
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#define RX_FIFO_THRESHOLD 0x4
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#define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
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#define WRITE_FIELD(var, mask, shift, value) \
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(var = ((var & ~(mask)) | ((value) << (shift))))
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static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
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static unsigned int i2c_bus_num;
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static unsigned int i2c_bus_speed[] = {
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
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};
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static struct u8500_i2c_regs *i2c_dev[] = {
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(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
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(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
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(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
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(struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
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};
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static struct {
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int periph;
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int pcken;
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int kcken;
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} i2c_clock_bits[] = {
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{3, 3, 3}, /* I2C0 */
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{1, 2, 2}, /* I2C1 */
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{1, 6, 6}, /* I2C2 */
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{2, 0, 0}, /* I2C3 */
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};
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static void i2c_set_bit(void *reg, u32 mask)
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{
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writel(readl(reg) | mask, reg);
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}
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static void i2c_clr_bit(void *reg, u32 mask)
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{
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writel(readl(reg) & ~mask, reg);
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}
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static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
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{
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writel((readl(reg) & ~mask) | (value << shift), reg);
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}
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static int __i2c_set_bus_speed(unsigned int speed)
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{
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u32 value;
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struct u8500_i2c_regs *i2c_regs;
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i2c_regs = i2c_dev[i2c_bus_num];
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/* Select standard (100 kbps) speed mode */
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i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
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U8500_I2C_CR_SHIFT_SM, 0x0);
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/*
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* Set the Baud Rate Counter 2 value
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* Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
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* Foncycle = 0 (no digital filtering)
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*/
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value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
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i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
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U8500_I2C_BRCR_SHIFT_BRCNT2, value);
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/* ensure that BRCNT value is zero */
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i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
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U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
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return U8500_I2C_INPUT_FREQ/(value * 2);
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}
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/*
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* i2c_init - initialize the i2c bus
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*
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* speed: bus speed (in HZ)
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* slaveaddr: address of device in slave mode
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*
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* Slave mode is not implemented.
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*/
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void i2c_init(int speed, int slaveaddr)
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{
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struct u8500_i2c_regs *i2c_regs;
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debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
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u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
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i2c_clock_bits[i2c_bus_num].pcken,
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i2c_clock_bits[i2c_bus_num].kcken);
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i2c_regs = i2c_dev[i2c_bus_num];
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/* Disable the controller */
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i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
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/* Clear registers */
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writel(0, &i2c_regs->cr);
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writel(0, &i2c_regs->scr);
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writel(0, &i2c_regs->hsmcr);
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writel(0, &i2c_regs->tftr);
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writel(0, &i2c_regs->rftr);
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writel(0, &i2c_regs->dmar);
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i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
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/*
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* Set our own address.
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* Set slave address mode to 7 bit addressing mode
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*/
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i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
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i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
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U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
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/* Slave Data Set up Time */
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i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
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U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
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/* Disable the DMA sync logic */
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i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
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U8500_I2C_CR_SHIFT_DMA_SLE, 0);
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/* Disable interrupts */
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writel(0, &i2c_regs->imscr);
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/* Configure bus master mode */
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i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
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U8500_I2C_BUS_MASTER_MODE);
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/* Set FIFO threshold values */
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writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
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writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
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/* Enable the I2C Controller */
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i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
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bus_initialized[i2c_bus_num] = 1;
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}
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/*
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* loop_till_bit_clear - polls on a bit till it clears
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* ioreg: register where you want to check status
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* mask: bit mask for the bit you wish to check
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* timeout: timeout in ticks/s
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*/
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static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
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{
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unsigned long timebase = get_timer(0);
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do {
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if ((readl(io_reg) & mask) == 0x0UL)
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return 0;
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} while (get_timer(timebase) < timeout);
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debug("loop_till_bit_clear timed out\n");
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return -1;
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}
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/*
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* loop_till_bit_set - polls on a bit till it is set.
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* ioreg: register where you want to check status
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* mask: bit mask for the bit you wish to check
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* timeout: timeout in ticks/s
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*/
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static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
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{
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unsigned long timebase = get_timer(0);
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do {
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if ((readl(io_reg) & mask) != 0x0UL)
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return 0;
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} while (get_timer(timebase) < timeout);
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debug("loop_till_bit_set timed out\n");
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return -1;
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}
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/*
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* flush_fifo - flush the I2C TX and RX FIFOs
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*/
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static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
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{
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int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
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/* Flush Tx FIFO */
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i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
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/* Flush Rx FIFO */
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i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
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while (counter--) {
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if (!(readl(&i2c_regs->cr) &
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(U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
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break;
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}
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return;
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}
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#ifdef DEBUG
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static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
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{
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int cause;
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printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
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cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
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U8500_I2C_SR_SHIFT_CAUSE;
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switch (cause) {
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case U8500_I2C_NACK_ADDR:
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printf("No Ack received after Slave Address xmission\n");
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break;
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case U8500_I2C_NACK_DATA:
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printf("Valid for MASTER_WRITE: No Ack received "
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"during data phase\n");
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break;
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case U8500_I2C_ACK_MCODE:
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printf("Master recv ack after xmission of master code"
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"in hs mode\n");
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break;
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case U8500_I2C_ARB_LOST:
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printf("Master Lost arbitration\n");
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break;
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case U8500_I2C_BERR_START:
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printf("Slave restarts\n");
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break;
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case U8500_I2C_BERR_STOP:
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printf("Slave reset\n");
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break;
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case U8500_I2C_OVFL:
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printf("Overflow\n");
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break;
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default:
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printf("Unknown error type\n");
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}
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}
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#endif
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/*
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* i2c_abort - called when a I2C transaction failed
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*/
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static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
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{
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#ifdef DEBUG
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print_abort_reason(i2c_regs);
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#endif
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/* flush RX and TX fifos */
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flush_fifo(i2c_regs);
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/* Acknowledge the Master Transaction Done */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
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/* Acknowledge the Master Transaction Done Without Stop */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
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i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
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}
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/*
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* write addr, alias index, to I2C bus.
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*/
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static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
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{
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while (alen--) {
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/* Wait until the Tx Fifo is not full */
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if (loop_till_bit_clear((void *)&i2c_regs->risr,
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U8500_I2C_INT_TXFF,
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U8500_I2C_ENDAD_COUNTER)) {
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i2c_abort(i2c_regs);
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return -1;
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}
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/* MSB first */
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writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
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}
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return 0;
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}
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/*
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* Internal simplified read function:
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* i2c_regs: Pointer to I2C registers for current bus
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one register)
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* value: Where to put the data
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*
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* Returns: 0 on success, not 0 on failure
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*/
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static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
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uint addr, int alen, uchar *value)
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{
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u32 mcr = 0;
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/* Set the address mode to 7 bit */
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WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
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/* Store the slave address in the master control register */
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WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
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if (alen != 0) {
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/* Master write operation */
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mcr &= ~(U8500_I2C_MCR_OP);
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/* Configure the Frame length to one byte */
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WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
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U8500_I2C_MCR_SHIFT_LENGTH, 1);
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/* Repeated start, no stop */
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mcr &= ~(U8500_I2C_MCR_STOP);
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/* Write Master Control Register */
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writel(mcr, &i2c_regs->mcr);
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/* send addr/index */
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if (i2c_write_addr(i2c_regs, addr, alen) != 0)
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return -1;
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/* Check for the Master Transaction Done Without Stop */
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if (loop_till_bit_set((void *)&i2c_regs->risr,
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U8500_I2C_INT_MTDWS,
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U8500_I2C_ENDAD_COUNTER)) {
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return -1;
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}
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/* Acknowledge the Master Transaction Done Without Stop */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
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}
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/* Master control configuration for read operation */
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mcr |= U8500_I2C_MCR_OP;
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/* Configure the STOP condition, we read only one byte */
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mcr |= U8500_I2C_MCR_STOP;
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/* Set the frame length to one byte, we support only 1 byte reads */
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WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
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i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
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U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
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/*
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* receive_data_polling
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*/
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/* Wait until the Rx FIFO is not empty */
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if (loop_till_bit_clear((void *)&i2c_regs->risr,
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U8500_I2C_INT_RXFE,
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U8500_I2C_ENDAD_COUNTER))
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return -1;
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/* Read the data byte from Rx FIFO */
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*value = readb(&i2c_regs->rfr);
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/* Wait until the work is done */
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if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
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U8500_I2C_ENDAD_COUNTER))
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return -1;
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/* Acknowledge the Master Transaction Done */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
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/* If MTD is set, Master Transaction Done Without Stop is set too */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
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return 0;
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}
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/*
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* Internal simplified write function:
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* i2c_regs: Pointer to I2C registers for current bus
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* chip: I2C chip address, range 0..127
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* addr: Memory (register) address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one register)
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* data: Where to read the data
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* len: How many bytes to write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
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int alen, u8 *data, int len)
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{
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int i;
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u32 mcr = 0;
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/* Set the address mode to 7 bit */
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WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
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/* Store the slave address in the master control register */
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WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
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/* Write operation */
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mcr &= ~(U8500_I2C_MCR_OP);
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/* Current transaction is terminated by STOP condition */
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mcr |= U8500_I2C_MCR_STOP;
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/* Frame length: addr byte + len */
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WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
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(alen + len));
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/* Write MCR register */
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writel(mcr, &i2c_regs->mcr);
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if (i2c_write_addr(i2c_regs, addr, alen) != 0)
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return -1;
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for (i = 0; i < len; i++) {
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/* Wait until the Tx FIFO is not full */
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if (loop_till_bit_clear((void *)&i2c_regs->risr,
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U8500_I2C_INT_TXFF,
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U8500_I2C_ENDAD_COUNTER))
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return -1;
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/* it is a 32 bit register with upper 24 reserved R/O */
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writeb(data[i], &i2c_regs->tfr);
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}
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/* Check for Master Transaction Done */
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if (loop_till_bit_set((void *)&i2c_regs->risr,
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U8500_I2C_INT_MTD,
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U8500_I2C_ENDAD_COUNTER)) {
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printf("i2c_write_byte error2: risr %08x\n",
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i2c_regs->risr);
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return -1;
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}
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/* Acknowledge Master Transaction Done */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
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/* Acknowledge Master Transaction Done Without Stop */
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i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Probe the given I2C chip address. Returns 0 if a chip responded,
|
|
* not 0 on failure.
|
|
*/
|
|
int i2c_probe(uchar chip)
|
|
{
|
|
u32 mcr = 0;
|
|
struct u8500_i2c_regs *i2c_regs;
|
|
|
|
if (chip == CONFIG_SYS_I2C_SLAVE)
|
|
return 1;
|
|
|
|
i2c_regs = i2c_dev[i2c_bus_num];
|
|
|
|
/* Set the address mode to 7 bit */
|
|
WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
|
|
|
|
/* Store the slave address in the master control register */
|
|
WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
|
|
|
|
/* Read operation */
|
|
mcr |= U8500_I2C_MCR_OP;
|
|
|
|
/* Set the frame length to one byte */
|
|
WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
|
|
|
|
/* Current transaction is terminated by STOP condition */
|
|
mcr |= U8500_I2C_MCR_STOP;
|
|
|
|
/* Write MCR register */
|
|
writel(mcr, &i2c_regs->mcr);
|
|
|
|
/* Wait until the Rx Fifo is not empty */
|
|
if (loop_till_bit_clear((void *)&i2c_regs->risr,
|
|
U8500_I2C_INT_RXFE,
|
|
U8500_I2C_ENDAD_COUNTER)) {
|
|
i2c_abort(i2c_regs);
|
|
return -1;
|
|
}
|
|
|
|
flush_fifo(i2c_regs);
|
|
|
|
/* Acknowledge the Master Transaction Done */
|
|
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
|
|
|
|
/* Acknowledge the Master Transaction Done Without Stop */
|
|
i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Read/Write interface:
|
|
* chip: I2C chip address, range 0..127
|
|
* addr: Memory (register) address within the chip
|
|
* alen: Number of bytes to use for addr (typically 1, 2 for larger
|
|
* memories, 0 for register type devices with only one
|
|
* register)
|
|
* buffer: Where to read/write the data
|
|
* len: How many bytes to read/write
|
|
*
|
|
* Returns: 0 on success, not 0 on failure
|
|
*/
|
|
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|
{
|
|
int i;
|
|
int rc;
|
|
struct u8500_i2c_regs *i2c_regs;
|
|
|
|
if (alen > 2) {
|
|
debug("I2C read: addr len %d not supported\n", alen);
|
|
return 1;
|
|
}
|
|
|
|
i2c_regs = i2c_dev[i2c_bus_num];
|
|
|
|
for (i = 0; i < len; i++) {
|
|
rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
|
|
if (rc != 0) {
|
|
debug("I2C read: I/O error: %d\n", rc);
|
|
i2c_abort(i2c_regs);
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
|
|
{
|
|
int rc;
|
|
struct u8500_i2c_regs *i2c_regs;
|
|
i2c_regs = i2c_dev[i2c_bus_num];
|
|
|
|
rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
|
|
len);
|
|
if (rc != 0) {
|
|
debug("I2C write: I/O error\n");
|
|
i2c_abort(i2c_regs);
|
|
return rc;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int i2c_set_bus_num(unsigned int bus)
|
|
{
|
|
if (bus > ARRAY_SIZE(i2c_dev) - 1) {
|
|
debug("i2c_set_bus_num: only up to bus %d supported\n",
|
|
ARRAY_SIZE(i2c_dev)-1);
|
|
return -1;
|
|
}
|
|
|
|
i2c_bus_num = bus;
|
|
|
|
if (!bus_initialized[i2c_bus_num])
|
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i2c_set_bus_speed(unsigned int speed)
|
|
{
|
|
|
|
if (speed > U8500_I2C_MAX_STANDARD_SCL) {
|
|
debug("i2c_set_bus_speed: only up to %d supported\n",
|
|
U8500_I2C_MAX_STANDARD_SCL);
|
|
return -1;
|
|
}
|
|
|
|
/* sets as side effect i2c_bus_speed[i2c_bus_num] */
|
|
i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
unsigned int i2c_get_bus_num(void)
|
|
{
|
|
return i2c_bus_num;
|
|
}
|
|
|
|
unsigned int i2c_get_bus_speed(void)
|
|
{
|
|
return i2c_bus_speed[i2c_bus_num];
|
|
}
|