mirror of
https://github.com/AsahiLinux/u-boot
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702e6014f1
Also drop a few files referring to no longer / not yet supported boards. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Jason Jin <jason.jin@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
84 lines
2.6 KiB
Text
84 lines
2.6 KiB
Text
Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
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1. Board Description
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The mvBL-M7 is a 120x120mm single board computing platform
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with strong focus on stereo image processing applications.
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Power Supply is either VDC 12-48V or Pover over Ethernet (PoE)
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on any port (requires add-on board).
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2 System Components
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2.1 CPU
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Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
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512MByte DDR-II memory @ 133MHz.
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8 MByte Nor Flash on local bus.
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2 Vitesse VSC8601 RGMII ethernet Phys.
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1 USB host controller over ULPI I/F.
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2 serial ports. Console running on ttyS0 @ 115200 8N1.
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1 SD-Card slot connected to SPI.
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System configuration (HRCW) is taken from I2C EEPROM.
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2.2 PCI
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A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
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2.3 FPGA
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Altera Cyclone-II EP2C20/35 with PCI DMA engines.
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Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
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Utilizes another 256MB DDR-II memory and 32-128MB Nand Flash.
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2.3.1 I/O @ FPGA
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2x8 Outputs : Infineon High-Side Switches to Main Supply.
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2x8 Inputs : Programmable input threshold + trigger capabilities
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2 dedicated flash interfaces for illuminator boards.
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Cross trigger for chaining several boards.
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2.4 I2C
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Bus1:
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MAX5381 DAC @ 0x60 for 1st digital input threshold.
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LM75 @ 0x90 for temperature monitoring.
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EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
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1st image sensor interface (slave addresses depend on sensor)
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Bus2:
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MAX5381 DAC @ 0x60 for 2nd digital input threshold.
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2nd image sensor interface (slave addresses depend on sensor)
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3 Flash layout.
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reset vector is 0xFFF00100, i.e. "HIGHBOOT".
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FF800000 environment
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FF802000 redundant environment
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FF804000 u-boot script image
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FF806000 redundant u-boot script image
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FF808000 device tree blob
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FF80A000 redundant device tree blob
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FF80C000 tbd.
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FF80E000 tbd.
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FF810000 kernel
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FFC00000 root FS
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FFF00000 u-boot
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FFF80000 FPGA raw bit file
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mtd partitions are propagated to linux kernel via device tree blob.
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4 Booting
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On startup the bootscript @ FF804000 is executed. This script can be
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exchanged easily. Default boot mode is "boot from flash", i.e. system
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works stand-alone.
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This behaviour depends on some environment variables :
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"netboot" : yes ->try dhcp/bootp and boot from network.
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A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
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DHCP server configuration, e.g. to provide different images to
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different devices.
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During netboot the system tries to get 3 image files:
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1. Kernel - name + data is given during BOOTP.
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2. Initrd - name is stored in "initrd_name"
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3. device tree blob - name is stored in "dtb_name"
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Fallback files are the flash versions.
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