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Xilinx LocalLink Tri-Mode Ether MAC driver can be used by Xilinx Microblaze or Xilinx ppc405/440 in SDMA and FIFO mode. DCR or XPS bus can be used. The driver uses and requires MII and PHYLIB. CP: 4 warnings: 'Use of volatile is usually wrong' I won't fix this, because it depends on the network driver subsystem. Reported-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Stephan Linz <linz@li-pro.net>
122 lines
4.4 KiB
C
122 lines
4.4 KiB
C
/*
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* Xilinx xps_ll_temac ethernet driver for u-boot
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*
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* FIFO sub-controller interface
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*
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* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 - 2011 PetaLogix
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*
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* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
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* Copyright (C) 2008 Nissin Systems Co.,Ltd.
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* March 2008 created
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_ll_temac.pdf
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* [A]: [0]/application_notes/xapp1041.pdf
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*/
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#ifndef _XILINX_LL_TEMAC_FIFO_
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#define _XILINX_LL_TEMAC_FIFO_
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#include <net.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#if !defined(__BIG_ENDIAN)
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# error LL_TEMAC requires big endianess
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#endif
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/*
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* FIFO Register Definition
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*
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* Used for memory mapped access from and to (Rd/Td) the LocalLink (LL)
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* Tri-Mode Ether MAC (TEMAC) via the 2 kb full duplex FIFO Controller,
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* one for each.
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*
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* [1]: [0]/ip_documentation/xps_ll_fifo.pdf
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* page 10, Registers Definition
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*/
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struct fifo_ctrl {
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u32 isr; /* Interrupt Status Register (RW) */
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u32 ier; /* Interrupt Enable Register (RW) */
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u32 tdfr; /* Transmit Data FIFO Reset (WO) */
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u32 tdfv; /* Transmit Data FIFO Vacancy (RO) */
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u32 tdfd; /* Transmit Data FIFO 32bit wide Data write port (WO) */
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u32 tlf; /* Transmit Length FIFO (WO) */
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u32 rdfr; /* Receive Data FIFO Reset (WO) */
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u32 rdfo; /* Receive Data FIFO Occupancy (RO) */
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u32 rdfd; /* Receive Data FIFO 32bit wide Data read port (RO) */
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u32 rlf; /* Receive Length FIFO (RO) */
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u32 llr; /* LocalLink Reset (WO) */
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};
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/* Interrupt Status Register (ISR), [1] p11 */
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#define LL_FIFO_ISR_RPURE (1 << 31) /* Receive Packet Underrun Read Err */
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#define LL_FIFO_ISR_RPORE (1 << 30) /* Receive Packet Overrun Read Err */
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#define LL_FIFO_ISR_RPUE (1 << 29) /* Receive Packet Underrun Error */
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#define LL_FIFO_ISR_TPOE (1 << 28) /* Transmit Packet Overrun Error */
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#define LL_FIFO_ISR_TC (1 << 27) /* Transmit Complete */
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#define LL_FIFO_ISR_RC (1 << 26) /* Receive Complete */
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#define LL_FIFO_ISR_TSE (1 << 25) /* Transmit Size Error */
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#define LL_FIFO_ISR_TRC (1 << 24) /* Transmit Reset Complete */
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#define LL_FIFO_ISR_RRC (1 << 23) /* Receive Reset Complete */
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/* Interrupt Enable Register (IER), [1] p12/p13 */
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#define LL_FIFO_IER_RPURE (1 << 31) /* Receive Packet Underrun Read Err */
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#define LL_FIFO_IER_RPORE (1 << 30) /* Receive Packet Overrun Read Err */
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#define LL_FIFO_IER_RPUE (1 << 29) /* Receive Packet Underrun Error */
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#define LL_FIFO_IER_TPOE (1 << 28) /* Transmit Packet Overrun Error */
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#define LL_FIFO_IER_TC (1 << 27) /* Transmit Complete */
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#define LL_FIFO_IER_RC (1 << 26) /* Receive Complete */
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#define LL_FIFO_IER_TSE (1 << 25) /* Transmit Size Error */
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#define LL_FIFO_IER_TRC (1 << 24) /* Transmit Reset Complete */
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#define LL_FIFO_IER_RRC (1 << 23) /* Receive Reset Complete */
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/* Transmit Data FIFO Reset (TDFR), [1] p13/p14 */
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#define LL_FIFO_TDFR_KEY 0x000000A5UL
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/* Transmit Data FIFO Vacancy (TDFV), [1] p14 */
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#define LL_FIFO_TDFV_POS 0
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#define LL_FIFO_TDFV_MASK (0x000001FFUL << LL_FIFO_TDFV_POS)
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/* Transmit Length FIFO (TLF), [1] p16/p17 */
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#define LL_FIFO_TLF_POS 0
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#define LL_FIFO_TLF_MASK (0x000007FFUL << LL_FIFO_TLF_POS)
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#define LL_FIFO_TLF_MIN ((4 * sizeof(u32)) & LL_FIFO_TLF_MASK)
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#define LL_FIFO_TLF_MAX ((510 * sizeof(u32)) & LL_FIFO_TLF_MASK)
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/* Receive Data FIFO Reset (RDFR), [1] p15 */
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#define LL_FIFO_RDFR_KEY 0x000000A5UL
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/* Receive Data FIFO Occupancy (RDFO), [1] p16 */
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#define LL_FIFO_RDFO_POS 0
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#define LL_FIFO_RDFO_MASK (0x000001FFUL << LL_FIFO_RDFO_POS)
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/* Receive Length FIFO (RLF), [1] p17/p18 */
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#define LL_FIFO_RLF_POS 0
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#define LL_FIFO_RLF_MASK (0x000007FFUL << LL_FIFO_RLF_POS)
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#define LL_FIFO_RLF_MIN ((4 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
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#define LL_FIFO_RLF_MAX ((510 * sizeof(uint32)) & LL_FIFO_RLF_MASK)
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/* LocalLink Reset (LLR), [1] p18 */
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#define LL_FIFO_LLR_KEY 0x000000A5UL
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/* reset FIFO and IRQ, disable interrupts */
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int ll_temac_reset_fifo(struct eth_device *dev);
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/* receive buffered data from FIFO (polling ISR) */
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int ll_temac_recv_fifo(struct eth_device *dev);
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/* send buffered data to FIFO */
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int ll_temac_send_fifo(struct eth_device *dev, volatile void *packet,
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int length);
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#endif /* _XILINX_LL_TEMAC_FIFO_ */
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