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32bb34a768
Fix: 4xx_uart.c: In function 'get_serial_clock': 4xx_uart.c:204:6: warning: variable 'tmp' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de>
307 lines
9 KiB
C
307 lines
9 KiB
C
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* This source code is dual-licensed. You may use it under the terms of the
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* GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*/
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#include <common.h>
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#include <commproc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#include <asm/ppc4xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405EX) || defined(CONFIG_440)
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#if defined(CONFIG_440)
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#if defined(CONFIG_440GP)
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#define CR0_MASK 0x3fff0000
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#define CR0_EXTCLK_ENA 0x00600000
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#define CR0_UDIV_POS 16
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#define UDIV_SUBTRACT 1
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#define UART0_SDR CPC0_CR0
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#define MFREG(a, d) d = mfdcr(a)
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#define MTREG(a, d) mtdcr(a, d)
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#else /* #if defined(CONFIG_440GP) */
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/* all other 440 PPC's access clock divider via sdr register */
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#define CR0_MASK 0xdfffffff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR SDR0_UART0
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#define UART1_SDR SDR0_UART1
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART2_SDR SDR0_UART2
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UART3_SDR SDR0_UART3
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#endif
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#endif /* #if defined(CONFIG_440GP) */
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#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#elif defined(CONFIG_405EX)
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#define MFREG(a, d) mfsdr(a, d)
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#define MTREG(a, d) mtsdr(a, d)
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#define CR0_MASK 0x000000ff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#define UDIV_SUBTRACT 0
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#define UART0_SDR SDR0_UART0
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#define UART1_SDR SDR0_UART1
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#else /* CONFIG_405GP || CONFIG_405CR */
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#define CR0_MASK 0x00001fff
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#define CR0_EXTCLK_ENA 0x000000c0
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#define CR0_UDIV_POS 1
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#define UDIV_MAX 32
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#endif
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#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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#error "External serial clock not supported on AMCC PPC405EP!"
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#endif
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#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
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defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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/*
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* For some SoC's, the cpu clock is on divider chain A, UART on
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* divider chain B ... so cpu clock is irrelevant. Get the
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* "optimized" values that are subject to the 1/2 opb clock
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* constraint.
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*/
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static u16 serial_bdiv(int baudrate, u32 *udiv)
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{
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sys_info_t sysinfo;
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u32 div; /* total divisor udiv * bdiv */
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u32 umin; /* minimum udiv */
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u16 diff; /* smallest diff */
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u16 idiff; /* current diff */
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u16 ibdiv; /* current bdiv */
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u32 i;
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u32 est; /* current estimate */
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u32 max;
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#if defined(CONFIG_405EZ)
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u32 cpr_pllc;
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u32 plloutb;
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u32 reg;
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#endif
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get_sys_info(&sysinfo);
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#if defined(CONFIG_405EZ)
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/* check the pll feedback source */
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mfcpr(CPR0_PLLC, cpr_pllc);
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plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
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sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
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sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
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div = plloutb / (16 * baudrate); /* total divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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max = 256; /* highest possible */
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#else /* 405EZ */
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div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
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max = 32; /* highest possible */
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#endif /* 405EZ */
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*udiv = diff = max;
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/*
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* i is the test udiv value -- start with the largest
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* possible (max) to minimize serial clock and constrain
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* search to umin.
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*/
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for (i = max; i > umin; i--) {
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ibdiv = div / i;
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est = i * ibdiv;
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idiff = (est > div) ? (est - div) : (div - est);
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if (idiff == 0) {
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*udiv = i;
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break; /* can't do better */
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} else if (idiff < diff) {
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*udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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#if defined(CONFIG_405EZ)
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mfcpr(CPR0_PERD0, reg);
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reg &= ~0x0000ffff;
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reg |= ((*udiv - 0) << 8) | (*udiv - 0);
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mtcpr(CPR0_PERD0, reg);
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#endif
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return div / *udiv;
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}
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#endif /* #if (defined(CONFIG_405EP) ... */
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/*
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* This function returns the UART clock used by the common
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* NS16550 driver. Additionally the SoC internal divisors for
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* optimal UART baudrate are configured.
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*/
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int get_serial_clock(void)
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{
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u32 clk;
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u32 udiv;
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#if !defined(CONFIG_405EZ)
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u32 reg;
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#endif
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#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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PPC4xx_SYS_INFO sys_info;
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#endif
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/*
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* Programming of the internal divisors is SoC specific.
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* Let's handle this in some #ifdef's for the SoC's.
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*/
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#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
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reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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udiv = 1;
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reg |= CR0_EXTCLK_ENA;
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#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
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clk = gd->cpu_clk;
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#ifdef CONFIG_SYS_405_UART_ERRATA_59
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udiv = 31; /* Errata 59: stuck at 31 */
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#else /* CONFIG_SYS_405_UART_ERRATA_59 */
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{
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u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
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udiv = (clk + tmp / 2) / tmp;
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}
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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#endif /* CONFIG_SYS_405_UART_ERRATA_59 */
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#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (CPC0_CR0, reg);
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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#else
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clk = CONFIG_SYS_BASE_BAUD * 16;
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#endif
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#endif /* CONFIG_405CR */
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#if defined(CONFIG_405EP)
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{
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u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
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reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
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clk = gd->cpu_clk;
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udiv = (clk + tmp / 2) / tmp;
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if (udiv > UDIV_MAX) /* max. n bits for udiv */
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udiv = UDIV_MAX;
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}
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reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
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reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
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mtdcr(CPC0_UCR, reg);
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clk = CONFIG_SYS_BASE_BAUD * 16;
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#endif /* CONFIG_405EP */
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#if defined(CONFIG_405EX) || defined(CONFIG_440)
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MFREG(UART0_SDR, reg);
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reg &= ~CR0_MASK;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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reg |= CR0_EXTCLK_ENA;
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udiv = 1;
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clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
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clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
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#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
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/*
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* Configure input clock to baudrate generator for all
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* available serial ports here
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*/
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MTREG(UART0_SDR, reg);
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#if defined(UART1_SDR)
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MTREG(UART1_SDR, reg);
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#endif
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#if defined(UART2_SDR)
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MTREG(UART2_SDR, reg);
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#endif
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#if defined(UART3_SDR)
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MTREG(UART3_SDR, reg);
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#endif
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#endif /* CONFIG_405EX ... */
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#if defined(CONFIG_405EZ)
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clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
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#endif /* CONFIG_405EZ */
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/*
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* Correct UART frequency in bd-info struct now that
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* the UART divisor is available
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*/
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
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#else
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get_sys_info(&sys_info);
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gd->uart_clk = sys_info.freqUART / udiv;
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#endif
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return clk;
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}
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#endif /* CONFIG_405GP || CONFIG_405CR */
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