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b2eff0340d
There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we shall set the accurate interval according to 48Mhz for those controllers. Note: The first controller no need set it, but if set it, shall change tphy's pll at the same time. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Marek Vasut <marex@denx.de> |
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| .. | ||
| cdns3 | ||
| common | ||
| dwc3 | ||
| emul | ||
| eth | ||
| gadget | ||
| host | ||
| isp1760 | ||
| mtu3 | ||
| musb | ||
| musb-new | ||
| phy | ||
| ulpi | ||
| Kconfig | ||