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324 lines
8.2 KiB
C
324 lines
8.2 KiB
C
/*
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* Timing and Organization details of the Elpida parts used in OMAP4
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* SDPs and Panda
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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/*
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* This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
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* SDP and Panda. Since the parts used and geometry are identical for
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* SDP and Panda for a given OMAP4 revision, this information is kept
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* here instead of being in board directory. However the key functions
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* exported are weakly linked so that they can be over-ridden in the board
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* directory if there is a OMAP4 board in the future that uses a different
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* memory device or geometry.
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*
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* For any new board with different memory devices over-ride one or more
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* of the following functions as per the CONFIG flags you intend to enable:
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* - emif_get_reg_dump()
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* - emif_get_dmm_regs()
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* - emif_get_device_details()
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* - emif_get_device_timings()
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*/
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#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
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.sdram_config_init = 0x80000eb9,
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.sdram_config = 0x80001ab9,
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.ref_ctrl = 0x0000030c,
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.sdram_tim1 = 0x08648311,
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.sdram_tim2 = 0x101b06ca,
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.sdram_tim3 = 0x0048a19f,
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.read_idle_ctrl = 0x000501ff,
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.zq_config = 0x500b3214,
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.temp_alert_config = 0xd8016893,
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
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.emif_ddr_phy_ctlr_1 = 0x049ff808
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};
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const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
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.sdram_config_init = 0x80000eb1,
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.sdram_config = 0x80001ab1,
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.ref_ctrl = 0x000005cd,
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.sdram_tim1 = 0x10cb0622,
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.sdram_tim2 = 0x20350d52,
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.sdram_tim3 = 0x00b1431f,
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.read_idle_ctrl = 0x000501ff,
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.zq_config = 0x500b3214,
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.temp_alert_config = 0x58016893,
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
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.emif_ddr_phy_ctlr_1 = 0x049ff418
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};
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const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
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.sdram_config_init = 0x80800eb2,
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.sdram_config = 0x80801ab2,
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.ref_ctrl = 0x00000618,
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.sdram_tim1 = 0x10eb0662,
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.sdram_tim2 = 0x20370dd2,
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.sdram_tim3 = 0x00b1c33f,
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.read_idle_ctrl = 0x000501ff,
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.zq_config = 0x500b3215,
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.temp_alert_config = 0x58016893,
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
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.emif_ddr_phy_ctlr_1 = 0x049ff418
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};
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const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
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.sdram_config_init = 0x80000eb9,
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.sdram_config = 0x80001ab9,
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.ref_ctrl = 0x00000618,
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.sdram_tim1 = 0x10eb0662,
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.sdram_tim2 = 0x20370dd2,
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.sdram_tim3 = 0x00b1c33f,
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.read_idle_ctrl = 0x000501ff,
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.zq_config = 0xd00b3214,
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.temp_alert_config = 0xd8016893,
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.emif_ddr_phy_ctlr_1_init = 0x049ffff5,
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.emif_ddr_phy_ctlr_1 = 0x049ff418
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};
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const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80540300,
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.is_ma_present = 0x0
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};
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const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80640300,
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.is_ma_present = 0x0
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};
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const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0xFF020100,
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.dmm_lisa_map_1 = 0,
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.dmm_lisa_map_2 = 0,
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.dmm_lisa_map_3 = 0x80640300,
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.is_ma_present = 0x1
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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{
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u32 omap4_rev = omap_revision();
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/* Same devices and geometry on both EMIFs */
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if (omap4_rev == OMAP4430_ES1_0)
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*regs = &emif_regs_elpida_380_mhz_1cs;
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else if (omap4_rev == OMAP4430_ES2_0)
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*regs = &emif_regs_elpida_200_mhz_2cs;
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else if (omap4_rev < OMAP4470_ES1_0)
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*regs = &emif_regs_elpida_400_mhz_2cs;
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else
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*regs = &emif_regs_elpida_400_mhz_1cs;
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}
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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__attribute__((weak, alias("emif_get_reg_dump_sdp")));
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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{
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u32 omap_rev = omap_revision();
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if (omap_rev == OMAP4430_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
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else if (omap_rev < OMAP4460_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
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else
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*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
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#else
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static const struct lpddr2_device_details elpida_2G_S4_details = {
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.type = LPDDR2_TYPE_S4,
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.density = LPDDR2_DENSITY_2Gb,
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.io_width = LPDDR2_IO_WIDTH_32,
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.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
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};
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static const struct lpddr2_device_details elpida_4G_S4_details = {
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.type = LPDDR2_TYPE_S4,
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.density = LPDDR2_DENSITY_4Gb,
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.io_width = LPDDR2_IO_WIDTH_32,
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.manufacturer = LPDDR2_MANUFACTURER_ELPIDA
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};
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struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
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struct lpddr2_device_details *lpddr2_dev_details)
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{
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u32 omap_rev = omap_revision();
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/* EMIF1 & EMIF2 have identical configuration */
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if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
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&& (cs == CS1)) {
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/* Nothing connected on CS1 for 4430/4470 ES1.0 */
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return NULL;
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} else if (omap_rev < OMAP4470_ES1_0) {
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/* In all other 4430/4460 cases Elpida 2G device */
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*lpddr2_dev_details = elpida_2G_S4_details;
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} else {
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/* 4470: 4G device */
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*lpddr2_dev_details = elpida_4G_S4_details;
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}
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return lpddr2_dev_details;
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}
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struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
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struct lpddr2_device_details *lpddr2_dev_details)
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__attribute__((weak, alias("emif_get_device_details_sdp")));
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#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
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#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
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.max_freq = 400000000,
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.RL = 6,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
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.max_freq = 333000000,
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.RL = 5,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
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.max_freq = 200000000,
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.RL = 3,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 20,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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static const struct lpddr2_min_tck min_tck_elpida = {
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.tRL = 3,
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.tRP_AB = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRAS_MIN = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
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&timings_elpida_200_mhz,
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&timings_elpida_333_mhz,
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&timings_elpida_400_mhz
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};
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static const struct lpddr2_device_timings elpida_2G_S4_timings = {
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.ac_timings = elpida_ac_timings,
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.min_tck = &min_tck_elpida,
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};
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void emif_get_device_timings_sdp(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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{
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u32 omap_rev = omap_revision();
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/* Identical devices on EMIF1 & EMIF2 */
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*cs0_device_timings = &elpida_2G_S4_timings;
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if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
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*cs1_device_timings = NULL;
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else
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*cs1_device_timings = &elpida_2G_S4_timings;
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}
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void emif_get_device_timings(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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__attribute__((weak, alias("emif_get_device_timings_sdp")));
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#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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const struct lpddr2_mr_regs mr_regs = {
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
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.mr2 = 0x4,
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.mr3 = -1,
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.mr10 = MR10_ZQ_ZQINIT,
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.mr16 = MR16_REF_FULL_ARRAY
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};
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void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
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{
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*regs = &mr_regs;
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}
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__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
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{
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return 0;
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}
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