mirror of
https://github.com/AsahiLinux/u-boot
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60607c9de0
Commit 1db7377a70 fixes the gen_atmel_mci driver
to be able to use multi block access for avr32. Therefore remove the setting
which forces single block access.
This also adds a huge performace gain for mmc access:
---8<---
Loading file "/boot/uImage" from mmc device 0:1
1830666 bytes read in 1293 ms (1.3 MiB/s)
--->8---
vs.
---8<---
Loading file "/boot/uImage" from mmc device 0:1
1830666 bytes read in 237 ms (7.4 MiB/s)
--->8---
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: haavard.skinnemoen@atmel.com
Cc: hans-christian.egtvedt@atmel.com
Cc: mpfj@mimc.co.uk
Cc: alex.raimondi@miromico.ch
Cc: julien.may@miromico.ch
Cc: egtvedt@samfundet.no
Cc: havard@skinnemoen.net
177 lines
5 KiB
C
177 lines
5 KiB
C
/*
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* Copyright (C) 2008 Miromico AG
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*
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* Configuration settings for the Miromico Hammerhead AVR32 board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AVR32
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_HAMMERHEAD
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#define CONFIG_SYS_HZ 1000
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/*
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* Set up the PLL to run at 125 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
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* and the PBA bus to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 25000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 5
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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#define CONFIG_SYS_CLKDIV_CPU 0
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#define CONFIG_SYS_CLKDIV_HSB 1
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#define CONFIG_SYS_CLKDIV_PBA 2
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM and NOR flash */
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#define CONFIG_SYS_NR_VM_REGIONS 2
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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#define CONFIG_HOSTNAME hammerhead
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"console=ttyS0 root=mtd1 rootfstype=jffs2"
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#define CONFIG_BOOTCOMMAND \
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"fsload; bootm"
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_AUTOBOOT
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press SPACE to abort autoboot in %d seconds\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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/*
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* After booting the board for the first time, new ethernet address
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* should be generated and assigned to the environment variables
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* "ethaddr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* BOOTP/DHCP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE 0x24000000
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#define CONFIG_SYS_INTRAM_SIZE 0x8000
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#define CONFIG_SYS_SDRAM_BASE 0x10000000
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "Hammerhead> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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