mirror of
https://github.com/AsahiLinux/u-boot
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219f4788d3
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value different than "> " which is vision2. I have Cc'd the maintainer here as I strongly suspect this is a bug rather than intentional behavior. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Stefano Babic <sbabic@denx.de>
252 lines
7.8 KiB
C
252 lines
7.8 KiB
C
/*
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* Configuation settings for the Freescale M5271EVB
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*
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* Based on MC5272C3 and r5200 board configs
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* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef _M5271EVB_H
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#define _M5271EVB_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_MCF52x2 /* define processor family */
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#define CONFIG_M5271 /* define processor type */
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#define CONFIG_M5271EVB /* define board type */
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#undef CONFIG_WATCHDOG /* disable watchdog */
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_ENV_OFFSET 0x4000
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#else
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#define CONFIG_ENV_ADDR 0xffe04000
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#endif
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#undef CONFIG_CMD_LOADS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
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#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_MII 1
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# define CONFIG_MII_INIT 1
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# define CONFIG_SYS_DISCOVER_PHY
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# define CONFIG_SYS_RX_ETH_BUFFER 8
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_SYS_FEC0_PINMUX 0
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# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
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# define MCFFEC_TOUT_LOOP 50000
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/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
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# ifndef CONFIG_SYS_DISCOVER_PHY
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# define FECDUPLEX FULL
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# define FECSPEED _100BASET
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# else
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# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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# endif
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# endif /* CONFIG_SYS_DISCOVER_PHY */
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#endif
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hw support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SPEED 80000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_OFFSET 0x00000300
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
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#define CONFIG_BOOTFILE "u-boot.bin"
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_RETRY_COUNT 5
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# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
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# define CONFIG_IPADDR 192.162.1.2
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# define CONFIG_NETMASK 255.255.255.0
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# define CONFIG_SERVERIP 192.162.1.1
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# define CONFIG_GATEWAYIP 192.162.1.1
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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#endif /* FEC_ENET */
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#define CONFIG_HOSTNAME M5271EVB
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"loadaddr=10000\0" \
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"uboot=u-boot.bin\0" \
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"load=tftp $loadaddr $uboot\0" \
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"upd=run load; run prog\0" \
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"prog=prot off ffe00000 ffe3ffff;" \
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"era ffe00000 ffe3ffff;" \
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"cp.b $loadaddr ffe00000 $filesize;" \
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"save\0" \
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""
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_MEMTEST_START 0x400
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#define CONFIG_SYS_MEMTEST_END 0x380000
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#define CONFIG_SYS_HZ 1000000
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/* Clock configuration
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* The external oscillator is a 25.000 MHz
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* CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
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* bus_clk = (cpu_clk/2) (fixed ratio)
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*
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* If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
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* match the new clock speed. Max cpu_clk is 150 MHz.
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*/
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#define CONFIG_SYS_CLK 100000000
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#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
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/*
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
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#define CONFIG_SYS_FLASH_BASE 0xffe00000
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#ifdef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_SYS_MONITOR_BASE 0x20000
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#else
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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/* FLASH organization */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_SIZE 0x200000
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
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CF_CACR_DISD | CF_CACR_INVI | \
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CF_CACR_CEIB | CF_CACR_DCM | \
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CF_CACR_EUSP)
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/* Chip Select 0 : Boot Flash */
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#define CONFIG_SYS_CS0_BASE 0xFFE00000
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#define CONFIG_SYS_CS0_MASK 0x001F0001
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#define CONFIG_SYS_CS0_CTRL 0x00001980
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/* Chip Select 1 : External SRAM */
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#define CONFIG_SYS_CS1_BASE 0x30000000
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#define CONFIG_SYS_CS1_MASK 0x00070001
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#define CONFIG_SYS_CS1_CTRL 0x00001900
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#endif /* _M5271EVB_H */
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