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https://github.com/AsahiLinux/u-boot
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387 lines
11 KiB
ArmAsm
387 lines
11 KiB
ArmAsm
/*------------------------------------------------------------------------------+
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*
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* This souce code has been made available to you by EuroDesign
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* (www.eurodsn.de). It's based on the original IBM source code, so
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* this follows:
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*
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* This source code is dual-licensed. You may use it under the terms of the
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* GNU General Public License version 2, or under the license below.
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*------------------------------------------------------------------------------- */
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#include <config.h>
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/**
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* ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
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*
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* IMPORTANT: For pass1 this code must run from cache since you can not
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* reliably change a peripheral banks timing register (pbxap) while running
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* code from that bank. For ex., since we are running from ROM on bank 0, we
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* can NOT execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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*
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* Bank 0 - Boot-Flash
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* Bank 1 - NAND-Flash
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* Bank 2 - ISA bus
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* Bank 3 - Second Flash
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* Bank 4 - USB controller
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*/
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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/*
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* We need the current boot up configuration to set correct
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* timings into internal flash and external flash
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*/
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mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
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0 0 -> 8 bit external ROM
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0 1 -> 16 bit internal ROM */
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addi r4,0,2
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srw r24,r24,r4 /* shift right r24 two positions */
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andi. r24,r24,0x06000
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/*
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* All calculations are based on 33MHz EBC clock.
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*
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* First, create a "very slow" timing (~250ns) with burst mode enabled
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* This is need for the external flash access
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*/
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lis r25,0x0800
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/* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
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ori r25,r25,0x0280
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/*
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* Second, create a fast timing:
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* 90ns first cycle - 3 clock access
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* and 90ns burst cycle, plus 1 clock after the last access
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* This is used for the internal access
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*/
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lis r26,0x8900
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/* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
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ori r26,r26,0x0280
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/*
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* We can't change settings on CS# if we currently use them.
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* -> load a few instructions into cache and run this code from cache
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*/
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mflr r4 /* save link register */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 10; used to prefetch */
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mtctr r4 /* 10 cache lines to fit this function
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in cache (gives us 8x10=80 instructions) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 10 cache lines */
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/*
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* Delay to ensure all accesses to ROM are complete before changing
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* bank 0 timings. 200usec should be enough.
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
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*/
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lis r3,0x0
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*-----------------------------------------------------------------------
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* Memory Bank 0 (BOOT-ROM) initialization
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* 0xFFEF00000....0xFFFFFFF
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* We only have to change the timing. Mapping is ok by boot-strapping
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*----------------------------------------------------------------------- */
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li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
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mtdcr EBC0_CFGADDR,r4
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mr r4,r26 /* assume internal fast flash is boot flash */
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cmpwi r24,0x2000 /* assumption true? ... */
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beq 1f /* ...yes! */
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mr r4,r25 /* ...no, use the slow variant */
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mr r25,r26 /* use this for the other flash */
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1:
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mtdcr EBC0_CFGDATA,r4 /* change timing now */
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li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
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mtdcr EBC0_CFGADDR,r4
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mfdcr r4,EBC0_CFGDATA
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lis r3,0x0001
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ori r3,r3,0x8000 /* allow reads and writes */
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or r4,r4,r3
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mtdcr EBC0_CFGDATA,r4
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/*-----------------------------------------------------------------------
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* Memory Bank 3 (Second-Flash) initialization
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* 0xF0000000...0xF01FFFFF -> 2MB
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*----------------------------------------------------------------------- */
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li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
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mtdcr EBC0_CFGADDR,r4
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mtdcr EBC0_CFGDATA,r2 /* change timing */
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li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0xF003
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ori r4,r4,0x8000
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/*
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* Consider boot configuration
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*/
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xori r24,r24,0x2000 /* invert current bus width */
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or r4,r4,r24
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mtdcr EBC0_CFGDATA,r4
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/*-----------------------------------------------------------------------
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* Memory Bank 1 (NAND-Flash) initialization
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* 0x77D00000...0x77DFFFFF -> 1MB
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* - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
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* - the setup time is 0ns
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* - the hold time is 15ns
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* ->
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* - TWT = 0
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* - CSN = 0
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* - OEN = 0
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* - WBN = 0
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* - WBF = 0
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* - TH = 1
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* ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
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*----------------------------------------------------------------------- */
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li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x0000
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ori r4,r4,0x0200
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mtdcr EBC0_CFGDATA,r4
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li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x77D1
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ori r4,r4,0x8000
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mtdcr EBC0_CFGDATA,r4
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/* USB init (without acceleration) */
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#ifndef CONFIG_ISP1161_PRESENT
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li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x0180
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ori r4,r4,0x5940
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mtdcr EBC0_CFGDATA,r4
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#endif
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/*-----------------------------------------------------------------------
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* Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
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* 0x78000000...0x7BFFFFFF -> 64 MB
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* Wir arbeiten bei 33 MHz -> 30ns
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*-----------------------------------------------------------------------
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A7 (ppc notation) or A24 (standard notation) decides about
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the type of access:
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A7/A24=0 -> memory cycle
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A7/ /A24=1 -> I/O cycle
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*/
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li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
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mtdcr EBC0_CFGADDR,r4
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/*
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We emulate an ISA access
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1. Address active
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2. wait 0 EBC clocks -> CSN=0
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3. set CS#
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4. wait 0 EBC clock -> OEN/WBN=0
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5. set OE#/WE#
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6. wait 4 clocks (ca. 90ns) and for Ready signal
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7. hold for 4 clocks -> TH=4
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*/
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#if 1
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/* faster access to isa-bus */
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lis r4,0x0180
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ori r4,r4,0x5940
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#else
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lis r4,0x0100
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ori r4,r4,0x0340
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#endif
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mtdcr EBC0_CFGDATA,r4
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#ifdef IDE_USES_ISA_EMULATION
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li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
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mtdcr EBC0_CFGADDR,r25
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mtdcr EBC0_CFGDATA,r4
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#endif
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li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
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mtdcr EBC0_CFGADDR,r25
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mtdcr EBC0_CFGDATA,r4
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li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
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mtdcr EBC0_CFGADDR,r25
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mtdcr EBC0_CFGDATA,r4
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li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
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mtdcr EBC0_CFGADDR,r25
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lis r4,0x780B
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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/*
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* the other areas are only 1MiB in size
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*/
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lis r4,0x7401
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ori r4,r4,0xA000
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li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
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mtdcr EBC0_CFGADDR,r25
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lis r4,0x7401
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
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mtdcr EBC0_CFGADDR,r25
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lis r4,0x7411
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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#ifndef CONFIG_ISP1161_PRESENT
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li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
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mtdcr EBC0_CFGADDR,r25
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lis r4,0x7421
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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#endif
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#ifdef IDE_USES_ISA_EMULATION
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li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
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mtdcr EBC0_CFGADDR,r25
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lis r4,0x0000
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ori r4,r4,0x0000
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mtdcr EBC0_CFGDATA,r4
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#endif
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/*-----------------------------------------------------------------------
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* Memory bank 4: USB controller Philips ISP6111
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* 0x77C00000 ... 0x77CFFFFF
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*
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* The chip is connected to:
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* - CPU CS#4
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* - CPU IRQ#2
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* - CPU DMA 3
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*
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* Timing:
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* - command to first data: 300ns. Software must ensure this timing!
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* - Write pulse: 26ns
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* - Read pulse: 33ns
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* - read cycle time: 150ns
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* - write cycle time: 140ns
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*
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* Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
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*
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* |- 300ns --|
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* |---- 420ns ---|---- 420ns ---| cycle
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* CS ############:###____#######:###____#######
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* OE ############:####___#######:####___#######
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* WE ############:####__########:####__########
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*
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* ----> 2 clocks RD/WR pulses: 60ns
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* ----> CSN: 3 clock, 90ns
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* ----> OEN: 1 clocks (read cycle)
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* ----> WBN: 1 clocks (write cycle)
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* ----> WBE: 2 clocks
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* ----> TH: 7 clock, 210ns
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* ----> TWT: 7 clocks
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*----------------------------------------------------------------------- */
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#ifdef CONFIG_ISP1161_PRESENT
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li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x030D
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ori r4,r4,0x5E80
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mtdcr EBC0_CFGDATA,r4
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li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x77C1
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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#endif
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#ifndef IDE_USES_ISA_EMULATION
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/*-----------------------------------------------------------------------
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* Memory Bank 5 used for IDE access
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*
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* Timings for IDE Interface
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*
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* SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
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* 70 165 30 PIO-Mode 0, [ns]
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* 3 6 1 [Cycles] ----> AP=0x040C0200
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* 50 125 20 PIO-Mode 1, [ns]
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* 2 5 1 [Cycles] ----> AP=0x03080200
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* 30 100 15 PIO-Mode 2, [ns]
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* 1 4 1 [Cycles] ----> AP=0x02040200
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* 30 80 10 PIO-Mode 3, [ns]
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* 1 3 1 [Cycles] ----> AP=0x01840200
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* 25 70 10 PIO-Mode 4, [ns]
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* 1 3 1 [Cycles] ----> AP=0x01840200
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*
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*----------------------------------------------------------------------- */
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li r4,PB5AP
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x040C
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ori r4,r4,0x0200
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mtdcr EBC0_CFGDATA,r4
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li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
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mtdcr EBC0_CFGADDR,r4
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lis r4,0x7A01
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ori r4,r4,0xA000
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mtdcr EBC0_CFGDATA,r4
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#endif
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/*
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* External Peripheral Control Register
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*/
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li r4,EBC0_CFG
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mtdcr EBC0_CFGADDR,r4
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lis r4,0xB84E
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ori r4,r4,0xF000
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mtdcr EBC0_CFGDATA,r4
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/*
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* drive POST code
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*/
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lis r4,0x7900
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ori r4,r4,0x0080
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li r3,0x0001
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stb r3,0(r4) /* 01 -> external bus controller is initialized */
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nop /* pass2 DCR errata #8 */
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blr
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