mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 02:20:25 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
110 lines
2.5 KiB
C
110 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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DECLARE_GLOBAL_DATA_PTR;
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static u32 qca953x_get_xtal(void)
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{
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u32 val;
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val = ath79_get_bootstrap();
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if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
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return 40000000;
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else
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return 25000000;
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}
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int get_serial_clock(void)
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{
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return qca953x_get_xtal();
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}
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int get_clocks(void)
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{
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void __iomem *regs;
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u32 val, ctrl, xtal, pll, div;
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regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
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MAP_NOCACHE);
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xtal = qca953x_get_xtal();
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ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
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val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
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/* VCOOUT = XTAL * DIV_INT */
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div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
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& QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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pll = xtal / div;
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/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
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div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
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& QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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pll *= div;
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div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
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& QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (!div)
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div = 1;
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pll >>= div;
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/* CPU_CLK = PLLOUT / CPU_POST_DIV */
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div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
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& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
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gd->cpu_clk = pll / div;
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val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
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/* VCOOUT = XTAL * DIV_INT */
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div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
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& QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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pll = xtal / div;
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/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
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div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
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& QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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pll *= div;
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div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
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& QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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if (!div)
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div = 1;
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pll >>= div;
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/* DDR_CLK = PLLOUT / DDR_POST_DIV */
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div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
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& QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
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gd->mem_clk = pll / div;
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div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
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& QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
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if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
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/* AHB_CLK = DDR_CLK / AHB_POST_DIV */
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gd->bus_clk = gd->mem_clk / (div + 1);
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} else {
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/* AHB_CLK = CPU_CLK / AHB_POST_DIV */
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gd->bus_clk = gd->cpu_clk / (div + 1);
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}
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return 0;
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}
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ulong get_bus_freq(ulong dummy)
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{
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if (!gd->bus_clk)
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get_clocks();
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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if (!gd->mem_clk)
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get_clocks();
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return gd->mem_clk;
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}
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