mirror of
https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
1007 lines
25 KiB
C
1007 lines
25 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
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* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
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* (C) Copyright 2006 DENX Software Engineering
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <memalign.h>
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#include <nand.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <dm/device_compat.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <asm/gpio.h>
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#include <fdtdec.h>
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#include <bouncebuf.h>
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#include <dm.h>
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#include "tegra_nand.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define NAND_CMD_TIMEOUT_MS 10
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#define SKIPPED_SPARE_BYTES 4
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/* ECC bytes to be generated for tag data */
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#define TAG_ECC_BYTES 4
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static const struct udevice_id tegra_nand_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-nand",
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},
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{ /* sentinel */ }
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};
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/* 64 byte oob block info for large page (== 2KB) device
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*
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* OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
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* Skipped bytes(4)
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* Main area Ecc(36)
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* Tag data(20)
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* Tag data Ecc(4)
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*
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* Yaffs2 will use 16 tag bytes.
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*/
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static struct nand_ecclayout eccoob = {
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.eccbytes = 36,
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.eccpos = {
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4, 5, 6, 7, 8, 9, 10, 11, 12,
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13, 14, 15, 16, 17, 18, 19, 20, 21,
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22, 23, 24, 25, 26, 27, 28, 29, 30,
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31, 32, 33, 34, 35, 36, 37, 38, 39,
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},
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.oobavail = 20,
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.oobfree = {
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{
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.offset = 40,
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.length = 20,
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},
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}
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};
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enum {
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ECC_OK,
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ECC_TAG_ERROR = 1 << 0,
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ECC_DATA_ERROR = 1 << 1
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};
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/* Timing parameters */
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enum {
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FDT_NAND_MAX_TRP_TREA,
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FDT_NAND_TWB,
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FDT_NAND_MAX_TCR_TAR_TRR,
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FDT_NAND_TWHR,
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FDT_NAND_MAX_TCS_TCH_TALS_TALH,
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FDT_NAND_TWH,
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FDT_NAND_TWP,
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FDT_NAND_TRH,
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FDT_NAND_TADL,
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FDT_NAND_TIMING_COUNT
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};
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/* Information about an attached NAND chip */
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struct fdt_nand {
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struct nand_ctlr *reg;
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int enabled; /* 1 to enable, 0 to disable */
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struct gpio_desc wp_gpio; /* write-protect GPIO */
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s32 width; /* bit width, normally 8 */
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u32 timing[FDT_NAND_TIMING_COUNT];
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};
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struct nand_drv {
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struct nand_ctlr *reg;
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struct fdt_nand config;
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};
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struct tegra_nand_info {
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struct udevice *dev;
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struct nand_drv nand_ctrl;
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struct nand_chip nand_chip;
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};
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/**
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* Wait for command completion
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*
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* @param reg nand_ctlr structure
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* @return
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* 1 - Command completed
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* 0 - Timeout
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*/
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static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
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{
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u32 reg_val;
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int running;
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int i;
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for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
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if ((readl(®->command) & CMD_GO) ||
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!(readl(®->status) & STATUS_RBSY0) ||
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!(readl(®->isr) & ISR_IS_CMD_DONE)) {
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udelay(1);
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continue;
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}
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reg_val = readl(®->dma_mst_ctrl);
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/*
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* If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
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* is set, that means DMA engine is running.
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*
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* Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
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* is cleared, indicating DMA transfer completion.
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*/
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running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
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DMA_MST_CTRL_EN_B_ENABLE);
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if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
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return 1;
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udelay(1);
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}
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return 0;
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}
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/**
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* Read one byte from the chip
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*
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* @param mtd MTD device structure
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* @return data byte
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*
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* Read function for 8bit bus-width
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*/
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static uint8_t read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_drv *info;
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info = (struct nand_drv *)nand_get_controller_data(chip);
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writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
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&info->reg->command);
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if (!nand_waitfor_cmd_completion(info->reg))
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printf("Command timeout\n");
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return (uint8_t)readl(&info->reg->resp);
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}
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/**
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* Read len bytes from the chip into a buffer
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*
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* @param mtd MTD device structure
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* @param buf buffer to store data to
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* @param len number of bytes to read
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*
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* Read function for 8bit bus-width
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*/
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static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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int i, s;
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unsigned int reg;
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
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for (i = 0; i < len; i += 4) {
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s = (len - i) > 4 ? 4 : len - i;
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writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
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((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
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&info->reg->command);
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if (!nand_waitfor_cmd_completion(info->reg))
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puts("Command timeout during read_buf\n");
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reg = readl(&info->reg->resp);
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memcpy(buf + i, ®, s);
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}
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}
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/**
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* Check NAND status to see if it is ready or not
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*
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* @param mtd MTD device structure
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* @return
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* 1 - ready
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* 0 - not ready
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*/
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static int nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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int reg_val;
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struct nand_drv *info;
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info = (struct nand_drv *)nand_get_controller_data(chip);
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reg_val = readl(&info->reg->status);
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if (reg_val & STATUS_RBSY0)
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return 1;
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else
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return 0;
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}
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/* Dummy implementation: we don't support multiple chips */
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static void nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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switch (chipnr) {
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case -1:
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case 0:
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break;
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default:
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BUG();
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}
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}
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/**
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* Clear all interrupt status bits
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*
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* @param reg nand_ctlr structure
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*/
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static void nand_clear_interrupt_status(struct nand_ctlr *reg)
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{
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u32 reg_val;
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/* Clear interrupt status */
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reg_val = readl(®->isr);
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writel(reg_val, ®->isr);
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}
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/**
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* Send command to NAND device
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*
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* @param mtd MTD device structure
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* @param command the command to be sent
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* @param column the column address for this command, -1 if none
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* @param page_addr the page address for this command, -1 if none
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*/
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static void nand_command(struct mtd_info *mtd, unsigned int command,
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int column, int page_addr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_drv *info;
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info = (struct nand_drv *)nand_get_controller_data(chip);
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/*
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* Write out the command to the device.
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*
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* Only command NAND_CMD_RESET or NAND_CMD_READID will come
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* here before mtd->writesize is initialized.
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*/
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/* Emulate NAND_CMD_READOOB */
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if (command == NAND_CMD_READOOB) {
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assert(mtd->writesize != 0);
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column += mtd->writesize;
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command = NAND_CMD_READ0;
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}
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/* Adjust columns for 16 bit bus-width */
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if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
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column >>= 1;
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nand_clear_interrupt_status(info->reg);
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/* Stop DMA engine, clear DMA completion status */
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writel(DMA_MST_CTRL_EN_A_DISABLE
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| DMA_MST_CTRL_EN_B_DISABLE
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| DMA_MST_CTRL_IS_DMA_DONE,
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&info->reg->dma_mst_ctrl);
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/*
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* Program and erase have their own busy handlers
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* status and sequential in needs no delay
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*/
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switch (command) {
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case NAND_CMD_READID:
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writel(NAND_CMD_READID, &info->reg->cmd_reg1);
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writel(column & 0xFF, &info->reg->addr_reg1);
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writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
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&info->reg->command);
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break;
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case NAND_CMD_PARAM:
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writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
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writel(column & 0xFF, &info->reg->addr_reg1);
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writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
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&info->reg->command);
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break;
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case NAND_CMD_READ0:
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writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
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writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
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writel((page_addr << 16) | (column & 0xFFFF),
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&info->reg->addr_reg1);
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writel(page_addr >> 16, &info->reg->addr_reg2);
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return;
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case NAND_CMD_SEQIN:
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writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
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writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
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writel((page_addr << 16) | (column & 0xFFFF),
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&info->reg->addr_reg1);
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writel(page_addr >> 16,
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&info->reg->addr_reg2);
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return;
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case NAND_CMD_PAGEPROG:
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return;
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case NAND_CMD_ERASE1:
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writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
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writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
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writel(page_addr, &info->reg->addr_reg1);
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writel(CMD_GO | CMD_CLE | CMD_ALE |
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CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
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&info->reg->command);
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break;
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case NAND_CMD_ERASE2:
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return;
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case NAND_CMD_STATUS:
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writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
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writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
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| ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
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| CMD_CE0,
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&info->reg->command);
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break;
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case NAND_CMD_RESET:
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writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
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writel(CMD_GO | CMD_CLE | CMD_CE0,
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&info->reg->command);
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break;
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case NAND_CMD_RNDOUT:
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default:
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printf("%s: Unsupported command %d\n", __func__, command);
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return;
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}
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if (!nand_waitfor_cmd_completion(info->reg))
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printf("Command 0x%02X timeout\n", command);
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}
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/**
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* Check whether the pointed buffer are all 0xff (blank).
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*
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* @param buf data buffer for blank check
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* @param len length of the buffer in byte
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* @return
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* 1 - blank
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* 0 - non-blank
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*/
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static int blank_check(u8 *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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if (buf[i] != 0xFF)
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return 0;
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return 1;
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}
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/**
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* After a DMA transfer for read, we call this function to see whether there
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* is any uncorrectable error on the pointed data buffer or oob buffer.
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*
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* @param reg nand_ctlr structure
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* @param databuf data buffer
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* @param a_len data buffer length
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* @param oobbuf oob buffer
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* @param b_len oob buffer length
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* @return
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* ECC_OK - no ECC error or correctable ECC error
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* ECC_TAG_ERROR - uncorrectable tag ECC error
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* ECC_DATA_ERROR - uncorrectable data ECC error
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* ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
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*/
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static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
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int a_len, u8 *oobbuf, int b_len)
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{
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int return_val = ECC_OK;
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u32 reg_val;
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if (!(readl(®->isr) & ISR_IS_ECC_ERR))
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return ECC_OK;
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/*
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* Area A is used for the data block (databuf). Area B is used for
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* the spare block (oobbuf)
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*/
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reg_val = readl(®->dec_status);
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if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
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reg_val = readl(®->bch_dec_status_buf);
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/*
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* If uncorrectable error occurs on data area, then see whether
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* they are all FF. If all are FF, it's a blank page.
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* Not error.
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*/
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if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
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!blank_check(databuf, a_len))
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return_val |= ECC_DATA_ERROR;
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}
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if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
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reg_val = readl(®->bch_dec_status_buf);
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/*
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* If uncorrectable error occurs on tag area, then see whether
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* they are all FF. If all are FF, it's a blank page.
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* Not error.
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*/
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if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
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!blank_check(oobbuf, b_len))
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return_val |= ECC_TAG_ERROR;
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}
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return return_val;
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}
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/**
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* Set GO bit to send command to device
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*
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* @param reg nand_ctlr structure
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*/
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static void start_command(struct nand_ctlr *reg)
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{
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u32 reg_val;
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reg_val = readl(®->command);
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reg_val |= CMD_GO;
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writel(reg_val, ®->command);
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}
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/**
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* Clear command GO bit, DMA GO bit, and DMA completion status
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*
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* @param reg nand_ctlr structure
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*/
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static void stop_command(struct nand_ctlr *reg)
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{
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/* Stop command */
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writel(0, ®->command);
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/* Stop DMA engine and clear DMA completion status */
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writel(DMA_MST_CTRL_GO_DISABLE
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| DMA_MST_CTRL_IS_DMA_DONE,
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®->dma_mst_ctrl);
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}
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/**
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* Set up NAND bus width and page size
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*
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* @param info nand_info structure
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* @param *reg_val address of reg_val
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* @return 0 if ok, -1 on error
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*/
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static int set_bus_width_page_size(struct mtd_info *our_mtd,
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struct fdt_nand *config, u32 *reg_val)
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{
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if (config->width == 8)
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*reg_val = CFG_BUS_WIDTH_8BIT;
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else if (config->width == 16)
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*reg_val = CFG_BUS_WIDTH_16BIT;
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else {
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debug("%s: Unsupported bus width %d\n", __func__,
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config->width);
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return -1;
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}
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if (our_mtd->writesize == 512)
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*reg_val |= CFG_PAGE_SIZE_512;
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else if (our_mtd->writesize == 2048)
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*reg_val |= CFG_PAGE_SIZE_2048;
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else if (our_mtd->writesize == 4096)
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*reg_val |= CFG_PAGE_SIZE_4096;
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else {
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debug("%s: Unsupported page size %d\n", __func__,
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our_mtd->writesize);
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return -1;
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}
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return 0;
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}
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/**
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* Page read/write function
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*
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* @param mtd mtd info structure
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* @param chip nand chip info structure
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* @param buf data buffer
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* @param page page number
|
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* @param with_ecc 1 to enable ECC, 0 to disable ECC
|
|
* @param is_writing 0 for read, 1 for write
|
|
* @return 0 when successfully completed
|
|
* -EIO when command timeout
|
|
*/
|
|
static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
|
|
uint8_t *buf, int page, int with_ecc, int is_writing)
|
|
{
|
|
u32 reg_val;
|
|
int tag_size;
|
|
struct nand_oobfree *free = chip->ecc.layout->oobfree;
|
|
/* 4*128=512 (byte) is the value that our HW can support. */
|
|
ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
|
|
char *tag_ptr;
|
|
struct nand_drv *info;
|
|
struct fdt_nand *config;
|
|
unsigned int bbflags;
|
|
struct bounce_buffer bbstate, bbstate_oob;
|
|
|
|
if ((uintptr_t)buf & 0x03) {
|
|
printf("buf %p has to be 4-byte aligned\n", buf);
|
|
return -EINVAL;
|
|
}
|
|
|
|
info = (struct nand_drv *)nand_get_controller_data(chip);
|
|
config = &info->config;
|
|
if (set_bus_width_page_size(mtd, config, ®_val))
|
|
return -EINVAL;
|
|
|
|
/* Need to be 4-byte aligned */
|
|
tag_ptr = (char *)tag_buf;
|
|
|
|
stop_command(info->reg);
|
|
|
|
if (is_writing)
|
|
bbflags = GEN_BB_READ;
|
|
else
|
|
bbflags = GEN_BB_WRITE;
|
|
|
|
bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
|
|
bbflags);
|
|
writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
|
|
writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
|
|
|
|
/* Set ECC selection, configure ECC settings */
|
|
if (with_ecc) {
|
|
if (is_writing)
|
|
memcpy(tag_ptr, chip->oob_poi + free->offset,
|
|
chip->ecc.layout->oobavail + TAG_ECC_BYTES);
|
|
tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
|
|
reg_val |= (CFG_SKIP_SPARE_SEL_4
|
|
| CFG_SKIP_SPARE_ENABLE
|
|
| CFG_HW_ECC_CORRECTION_ENABLE
|
|
| CFG_ECC_EN_TAG_DISABLE
|
|
| CFG_HW_ECC_SEL_RS
|
|
| CFG_HW_ECC_ENABLE
|
|
| CFG_TVAL4
|
|
| (tag_size - 1));
|
|
|
|
if (!is_writing)
|
|
tag_size += SKIPPED_SPARE_BYTES;
|
|
bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
|
|
bbflags);
|
|
} else {
|
|
tag_size = mtd->oobsize;
|
|
reg_val |= (CFG_SKIP_SPARE_DISABLE
|
|
| CFG_HW_ECC_CORRECTION_DISABLE
|
|
| CFG_ECC_EN_TAG_DISABLE
|
|
| CFG_HW_ECC_DISABLE
|
|
| (tag_size - 1));
|
|
bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
|
|
tag_size, bbflags);
|
|
}
|
|
writel(reg_val, &info->reg->config);
|
|
writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
|
|
writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
|
|
writel(tag_size - 1, &info->reg->dma_cfg_b);
|
|
|
|
nand_clear_interrupt_status(info->reg);
|
|
|
|
reg_val = CMD_CLE | CMD_ALE
|
|
| CMD_SEC_CMD
|
|
| (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
|
|
| CMD_A_VALID
|
|
| CMD_B_VALID
|
|
| (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
|
|
| CMD_CE0;
|
|
if (!is_writing)
|
|
reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
|
|
else
|
|
reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
|
|
writel(reg_val, &info->reg->command);
|
|
|
|
/* Setup DMA engine */
|
|
reg_val = DMA_MST_CTRL_GO_ENABLE
|
|
| DMA_MST_CTRL_BURST_8WORDS
|
|
| DMA_MST_CTRL_EN_A_ENABLE
|
|
| DMA_MST_CTRL_EN_B_ENABLE;
|
|
|
|
if (!is_writing)
|
|
reg_val |= DMA_MST_CTRL_DIR_READ;
|
|
else
|
|
reg_val |= DMA_MST_CTRL_DIR_WRITE;
|
|
|
|
writel(reg_val, &info->reg->dma_mst_ctrl);
|
|
|
|
start_command(info->reg);
|
|
|
|
if (!nand_waitfor_cmd_completion(info->reg)) {
|
|
if (!is_writing)
|
|
printf("Read Page 0x%X timeout ", page);
|
|
else
|
|
printf("Write Page 0x%X timeout ", page);
|
|
if (with_ecc)
|
|
printf("with ECC");
|
|
else
|
|
printf("without ECC");
|
|
printf("\n");
|
|
return -EIO;
|
|
}
|
|
|
|
bounce_buffer_stop(&bbstate_oob);
|
|
bounce_buffer_stop(&bbstate);
|
|
|
|
if (with_ecc && !is_writing) {
|
|
memcpy(chip->oob_poi, tag_ptr,
|
|
SKIPPED_SPARE_BYTES);
|
|
memcpy(chip->oob_poi + free->offset,
|
|
tag_ptr + SKIPPED_SPARE_BYTES,
|
|
chip->ecc.layout->oobavail);
|
|
reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
|
|
1 << chip->page_shift,
|
|
(u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
|
|
chip->ecc.layout->oobavail);
|
|
if (reg_val & ECC_TAG_ERROR)
|
|
printf("Read Page 0x%X tag ECC error\n", page);
|
|
if (reg_val & ECC_DATA_ERROR)
|
|
printf("Read Page 0x%X data ECC error\n",
|
|
page);
|
|
if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
|
|
return -EIO;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Hardware ecc based page read function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param buf buffer to store read data
|
|
* @param page page number to read
|
|
* @return 0 when successfully completed
|
|
* -EIO when command timeout
|
|
*/
|
|
static int nand_read_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
|
|
{
|
|
return nand_rw_page(mtd, chip, buf, page, 1, 0);
|
|
}
|
|
|
|
/**
|
|
* Hardware ecc based page write function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param buf data buffer
|
|
*/
|
|
static int nand_write_page_hwecc(struct mtd_info *mtd,
|
|
struct nand_chip *chip, const uint8_t *buf, int oob_required,
|
|
int page)
|
|
{
|
|
nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* Read raw page data without ecc
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param buf buffer to store read data
|
|
* @param page page number to read
|
|
* @return 0 when successfully completed
|
|
* -EINVAL when chip->oob_poi is not double-word aligned
|
|
* -EIO when command timeout
|
|
*/
|
|
static int nand_read_page_raw(struct mtd_info *mtd,
|
|
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
|
|
{
|
|
return nand_rw_page(mtd, chip, buf, page, 0, 0);
|
|
}
|
|
|
|
/**
|
|
* Raw page write function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param buf data buffer
|
|
*/
|
|
static int nand_write_page_raw(struct mtd_info *mtd,
|
|
struct nand_chip *chip, const uint8_t *buf,
|
|
int oob_required, int page)
|
|
{
|
|
nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* OOB data read/write function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param page page number to read
|
|
* @param with_ecc 1 to enable ECC, 0 to disable ECC
|
|
* @param is_writing 0 for read, 1 for write
|
|
* @return 0 when successfully completed
|
|
* -EINVAL when chip->oob_poi is not double-word aligned
|
|
* -EIO when command timeout
|
|
*/
|
|
static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int page, int with_ecc, int is_writing)
|
|
{
|
|
u32 reg_val;
|
|
int tag_size;
|
|
struct nand_oobfree *free = chip->ecc.layout->oobfree;
|
|
struct nand_drv *info;
|
|
unsigned int bbflags;
|
|
struct bounce_buffer bbstate_oob;
|
|
|
|
if (((int)chip->oob_poi) & 0x03)
|
|
return -EINVAL;
|
|
info = (struct nand_drv *)nand_get_controller_data(chip);
|
|
if (set_bus_width_page_size(mtd, &info->config, ®_val))
|
|
return -EINVAL;
|
|
|
|
stop_command(info->reg);
|
|
|
|
/* Set ECC selection */
|
|
tag_size = mtd->oobsize;
|
|
if (with_ecc)
|
|
reg_val |= CFG_ECC_EN_TAG_ENABLE;
|
|
else
|
|
reg_val |= (CFG_ECC_EN_TAG_DISABLE);
|
|
|
|
reg_val |= ((tag_size - 1) |
|
|
CFG_SKIP_SPARE_DISABLE |
|
|
CFG_HW_ECC_CORRECTION_DISABLE |
|
|
CFG_HW_ECC_DISABLE);
|
|
writel(reg_val, &info->reg->config);
|
|
|
|
if (is_writing && with_ecc)
|
|
tag_size -= TAG_ECC_BYTES;
|
|
|
|
if (is_writing)
|
|
bbflags = GEN_BB_READ;
|
|
else
|
|
bbflags = GEN_BB_WRITE;
|
|
|
|
bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
|
|
bbflags);
|
|
writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
|
|
|
|
writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
|
|
|
|
writel(tag_size - 1, &info->reg->dma_cfg_b);
|
|
|
|
nand_clear_interrupt_status(info->reg);
|
|
|
|
reg_val = CMD_CLE | CMD_ALE
|
|
| CMD_SEC_CMD
|
|
| (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
|
|
| CMD_B_VALID
|
|
| CMD_CE0;
|
|
if (!is_writing)
|
|
reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
|
|
else
|
|
reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
|
|
writel(reg_val, &info->reg->command);
|
|
|
|
/* Setup DMA engine */
|
|
reg_val = DMA_MST_CTRL_GO_ENABLE
|
|
| DMA_MST_CTRL_BURST_8WORDS
|
|
| DMA_MST_CTRL_EN_B_ENABLE;
|
|
if (!is_writing)
|
|
reg_val |= DMA_MST_CTRL_DIR_READ;
|
|
else
|
|
reg_val |= DMA_MST_CTRL_DIR_WRITE;
|
|
|
|
writel(reg_val, &info->reg->dma_mst_ctrl);
|
|
|
|
start_command(info->reg);
|
|
|
|
if (!nand_waitfor_cmd_completion(info->reg)) {
|
|
if (!is_writing)
|
|
printf("Read OOB of Page 0x%X timeout\n", page);
|
|
else
|
|
printf("Write OOB of Page 0x%X timeout\n", page);
|
|
return -EIO;
|
|
}
|
|
|
|
bounce_buffer_stop(&bbstate_oob);
|
|
|
|
if (with_ecc && !is_writing) {
|
|
reg_val = (u32)check_ecc_error(info->reg, 0, 0,
|
|
(u8 *)(chip->oob_poi + free->offset),
|
|
chip->ecc.layout->oobavail);
|
|
if (reg_val & ECC_TAG_ERROR)
|
|
printf("Read OOB of Page 0x%X tag ECC error\n", page);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* OOB data read function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param page page number to read
|
|
*/
|
|
static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int page)
|
|
{
|
|
chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
|
|
nand_rw_oob(mtd, chip, page, 0, 0);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* OOB data write function
|
|
*
|
|
* @param mtd mtd info structure
|
|
* @param chip nand chip info structure
|
|
* @param page page number to write
|
|
* @return 0 when successfully completed
|
|
* -EINVAL when chip->oob_poi is not double-word aligned
|
|
* -EIO when command timeout
|
|
*/
|
|
static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int page)
|
|
{
|
|
chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
|
|
|
|
return nand_rw_oob(mtd, chip, page, 0, 1);
|
|
}
|
|
|
|
/**
|
|
* Set up NAND memory timings according to the provided parameters
|
|
*
|
|
* @param timing Timing parameters
|
|
* @param reg NAND controller register address
|
|
*/
|
|
static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
|
|
struct nand_ctlr *reg)
|
|
{
|
|
u32 reg_val, clk_rate, clk_period, time_val;
|
|
|
|
clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
|
|
CLOCK_ID_PERIPH) / 1000000;
|
|
clk_period = 1000 / clk_rate;
|
|
reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
|
|
TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
|
|
TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
|
|
time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
|
|
if (time_val > 2)
|
|
reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
|
|
TIMING_TCR_TAR_TRR_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
|
|
TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
|
|
time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
|
|
if (time_val > 1)
|
|
reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
|
|
TIMING_TCS_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
|
|
TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
|
|
TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
|
|
TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
|
|
reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
|
|
TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
|
|
writel(reg_val, ®->timing);
|
|
|
|
reg_val = 0;
|
|
time_val = timing[FDT_NAND_TADL] / clk_period;
|
|
if (time_val > 2)
|
|
reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
|
|
writel(reg_val, ®->timing2);
|
|
}
|
|
|
|
/**
|
|
* Decode NAND parameters from the device tree
|
|
*
|
|
* @param dev Driver model device
|
|
* @param config Device tree NAND configuration
|
|
* @return 0 if ok, -ve on error (FDT_ERR_...)
|
|
*/
|
|
static int fdt_decode_nand(struct udevice *dev, struct fdt_nand *config)
|
|
{
|
|
int err;
|
|
|
|
config->reg = (struct nand_ctlr *)dev_read_addr(dev);
|
|
config->enabled = dev_read_enabled(dev);
|
|
config->width = dev_read_u32_default(dev, "nvidia,nand-width", 8);
|
|
err = gpio_request_by_name(dev, "nvidia,wp-gpios", 0, &config->wp_gpio,
|
|
GPIOD_IS_OUT);
|
|
if (err)
|
|
return err;
|
|
err = dev_read_u32_array(dev, "nvidia,timing", config->timing,
|
|
FDT_NAND_TIMING_COUNT);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_probe(struct udevice *dev)
|
|
{
|
|
struct tegra_nand_info *tegra = dev_get_priv(dev);
|
|
struct nand_chip *nand = &tegra->nand_chip;
|
|
struct nand_drv *info = &tegra->nand_ctrl;
|
|
struct fdt_nand *config = &info->config;
|
|
struct mtd_info *our_mtd;
|
|
int ret;
|
|
|
|
if (fdt_decode_nand(dev, config)) {
|
|
printf("Could not decode nand-flash in device tree\n");
|
|
return -1;
|
|
}
|
|
if (!config->enabled)
|
|
return -1;
|
|
info->reg = config->reg;
|
|
nand->ecc.mode = NAND_ECC_HW;
|
|
nand->ecc.layout = &eccoob;
|
|
|
|
nand->options = LP_OPTIONS;
|
|
nand->cmdfunc = nand_command;
|
|
nand->read_byte = read_byte;
|
|
nand->read_buf = read_buf;
|
|
nand->ecc.read_page = nand_read_page_hwecc;
|
|
nand->ecc.write_page = nand_write_page_hwecc;
|
|
nand->ecc.read_page_raw = nand_read_page_raw;
|
|
nand->ecc.write_page_raw = nand_write_page_raw;
|
|
nand->ecc.read_oob = nand_read_oob;
|
|
nand->ecc.write_oob = nand_write_oob;
|
|
nand->ecc.strength = 1;
|
|
nand->select_chip = nand_select_chip;
|
|
nand->dev_ready = nand_dev_ready;
|
|
nand_set_controller_data(nand, &tegra->nand_ctrl);
|
|
|
|
/* Disable subpage writes as we do not provide ecc->hwctl */
|
|
nand->options |= NAND_NO_SUBPAGE_WRITE;
|
|
|
|
/* Adjust controller clock rate */
|
|
clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
|
|
|
|
/* Adjust timing for NAND device */
|
|
setup_timing(config->timing, info->reg);
|
|
|
|
dm_gpio_set_value(&config->wp_gpio, 1);
|
|
|
|
our_mtd = nand_to_mtd(nand);
|
|
ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
nand->ecc.size = our_mtd->writesize;
|
|
nand->ecc.bytes = our_mtd->oobsize;
|
|
|
|
ret = nand_scan_tail(our_mtd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = nand_register(0, our_mtd);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to register MTD: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(tegra_nand) = {
|
|
.name = "tegra-nand",
|
|
.id = UCLASS_MTD,
|
|
.of_match = tegra_nand_dt_ids,
|
|
.probe = tegra_probe,
|
|
.priv_auto = sizeof(struct tegra_nand_info),
|
|
};
|
|
|
|
void board_nand_init(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
|
DM_DRIVER_GET(tegra_nand), &dev);
|
|
if (ret && ret != -ENODEV)
|
|
pr_err("Failed to initialize %s. (error %d)\n", dev->name,
|
|
ret);
|
|
}
|