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https://github.com/AsahiLinux/u-boot
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6620377e4b
Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
146 lines
3.4 KiB
C
146 lines
3.4 KiB
C
/*
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* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
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*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Some init for sunxi platform.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <serial.h>
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#ifdef CONFIG_SPL_BUILD
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#include <spl.h>
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#endif
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <linux/compiler.h>
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#ifdef CONFIG_SPL_BUILD
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/* Pointer to the global data structure for SPL */
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DECLARE_GLOBAL_DATA_PTR;
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/* The sunxi internal brom will try to loader external bootloader
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* from mmc0, nand flash, mmc2.
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* Unfortunately we can't check how SPL was loaded so assume
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* it's always the first SD/MMC controller
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*/
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_MMC1;
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}
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/* No confirmation data available in SPL yet. Hardcode bootmode */
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u32 spl_boot_mode(void)
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{
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return MMCSD_MODE_RAW;
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}
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#endif
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int gpio_init(void)
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{
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#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
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sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
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sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
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#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
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sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
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sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
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#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
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sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
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sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
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sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
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#else
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#error Unsupported console port number. Please fix pin mux settings in board.c
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#endif
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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static const struct sunxi_wdog *wdog =
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&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
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/* Set the watchdog for its shortest interval (.5s) and wait */
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writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
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writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
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while (1);
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}
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/* do some early init */
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void s_init(void)
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{
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#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
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/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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#endif
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clock_init();
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timer_init();
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gpio_init();
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i2c_init_board();
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#ifdef CONFIG_SPL_BUILD
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gd = &gdata;
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preloader_console_init();
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#ifdef CONFIG_SPL_I2C_SUPPORT
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/* Needed early by sunxi_board_init if PMU is enabled */
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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#endif
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sunxi_board_init();
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#endif
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#ifdef CONFIG_CMD_NET
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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__maybe_unused int rc;
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#ifdef CONFIG_SUNXI_EMAC
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rc = sunxi_emac_initialize(bis);
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if (rc < 0) {
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printf("sunxi: failed to initialize emac\n");
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return rc;
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}
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#endif
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#ifdef CONFIG_SUNXI_GMAC
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rc = sunxi_gmac_initialize(bis);
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if (rc < 0) {
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printf("sunxi: failed to initialize gmac\n");
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return rc;
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}
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#endif
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return 0;
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}
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#endif
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