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6aa3b740c3
The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: Suman Anna <s-anna@ti.com>
902 lines
21 KiB
C
902 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments' K3 R5 Remoteproc driver
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*
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* Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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* Suman Anna <s-anna@ti.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <remoteproc.h>
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#include <errno.h>
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#include <clk.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include "ti_sci_proc.h"
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/*
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* R5F's view of this address can either be for ATCM or BTCM with the other
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* at address 0x0 based on loczrama signal.
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*/
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#define K3_R5_TCM_DEV_ADDR 0x41010000
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/* R5 TI-SCI Processor Configuration Flags */
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#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
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#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
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#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
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#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
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#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
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#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
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#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
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#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
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#define PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR 0x10000000
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/* Available from J7200 SoCs onwards */
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#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
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/* R5 TI-SCI Processor Control Flags */
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#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
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/* R5 TI-SCI Processor Status Flags */
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#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
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#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
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#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
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#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
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#define NR_CORES 2
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enum cluster_mode {
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CLUSTER_MODE_SPLIT = 0,
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CLUSTER_MODE_LOCKSTEP,
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};
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/**
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* struct k3_r5f_ip_data - internal data structure used for IP variations
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* @tcm_is_double: flag to denote the larger unified TCMs in certain modes
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* @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
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*/
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struct k3_r5f_ip_data {
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bool tcm_is_double;
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bool tcm_ecc_autoinit;
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};
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/**
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* struct k3_r5_mem - internal memory structure
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* @cpu_addr: MPU virtual address of the memory region
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* @bus_addr: Bus address used to access the memory region
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* @dev_addr: Device address from remoteproc view
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* @size: Size of the memory region
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*/
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struct k3_r5f_mem {
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void __iomem *cpu_addr;
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phys_addr_t bus_addr;
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u32 dev_addr;
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size_t size;
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};
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/**
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* struct k3_r5f_core - K3 R5 core structure
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* @dev: cached device pointer
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* @cluster: pointer to the parent cluster.
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* @reset: reset control handle
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* @tsp: TI-SCI processor control handle
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* @ipdata: cached pointer to R5F IP specific feature data
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* @mem: Array of available internal memories
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* @num_mem: Number of available memories
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* @atcm_enable: flag to control ATCM enablement
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* @btcm_enable: flag to control BTCM enablement
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* @loczrama: flag to dictate which TCM is at device address 0x0
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* @in_use: flag to tell if the core is already in use.
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*/
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struct k3_r5f_core {
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struct udevice *dev;
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struct k3_r5f_cluster *cluster;
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struct reset_ctl reset;
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struct ti_sci_proc tsp;
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struct k3_r5f_ip_data *ipdata;
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struct k3_r5f_mem *mem;
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int num_mems;
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u32 atcm_enable;
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u32 btcm_enable;
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u32 loczrama;
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bool in_use;
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};
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/**
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* struct k3_r5f_cluster - K3 R5F Cluster structure
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* @mode: Mode to configure the Cluster - Split or LockStep
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* @cores: Array of pointers to R5 cores within the cluster
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*/
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struct k3_r5f_cluster {
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enum cluster_mode mode;
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struct k3_r5f_core *cores[NR_CORES];
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};
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static bool is_primary_core(struct k3_r5f_core *core)
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{
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return core == core->cluster->cores[0];
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}
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static int k3_r5f_proc_request(struct k3_r5f_core *core)
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{
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struct k3_r5f_cluster *cluster = core->cluster;
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int i, ret;
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
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for (i = 0; i < NR_CORES; i++) {
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ret = ti_sci_proc_request(&cluster->cores[i]->tsp);
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if (ret)
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goto proc_release;
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}
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} else {
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ret = ti_sci_proc_request(&core->tsp);
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}
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return 0;
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proc_release:
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while (i >= 0) {
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ti_sci_proc_release(&cluster->cores[i]->tsp);
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i--;
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}
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return ret;
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}
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static void k3_r5f_proc_release(struct k3_r5f_core *core)
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{
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struct k3_r5f_cluster *cluster = core->cluster;
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int i;
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
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for (i = 0; i < NR_CORES; i++)
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ti_sci_proc_release(&cluster->cores[i]->tsp);
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else
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ti_sci_proc_release(&core->tsp);
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}
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static int k3_r5f_lockstep_release(struct k3_r5f_cluster *cluster)
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{
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int ret, c;
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dev_dbg(dev, "%s\n", __func__);
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for (c = NR_CORES - 1; c >= 0; c--) {
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ret = ti_sci_proc_power_domain_on(&cluster->cores[c]->tsp);
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if (ret)
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goto unroll_module_reset;
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}
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/* deassert local reset on all applicable cores */
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for (c = NR_CORES - 1; c >= 0; c--) {
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ret = reset_deassert(&cluster->cores[c]->reset);
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if (ret)
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goto unroll_local_reset;
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}
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return 0;
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unroll_local_reset:
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while (c < NR_CORES) {
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reset_assert(&cluster->cores[c]->reset);
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c++;
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}
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c = 0;
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unroll_module_reset:
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while (c < NR_CORES) {
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ti_sci_proc_power_domain_off(&cluster->cores[c]->tsp);
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c++;
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}
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return ret;
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}
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static int k3_r5f_split_release(struct k3_r5f_core *core)
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{
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int ret;
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dev_dbg(dev, "%s\n", __func__);
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ret = ti_sci_proc_power_domain_on(&core->tsp);
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if (ret) {
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dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
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ret);
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return ret;
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}
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ret = reset_deassert(&core->reset);
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if (ret) {
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dev_err(core->dev, "local-reset deassert failed, ret = %d\n",
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ret);
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if (ti_sci_proc_power_domain_off(&core->tsp))
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dev_warn(core->dev, "module-reset assert back failed\n");
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}
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return ret;
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}
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static int k3_r5f_prepare(struct udevice *dev)
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{
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struct k3_r5f_core *core = dev_get_priv(dev);
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struct k3_r5f_cluster *cluster = core->cluster;
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int ret = 0;
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dev_dbg(dev, "%s\n", __func__);
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
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ret = k3_r5f_lockstep_release(cluster);
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else
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ret = k3_r5f_split_release(core);
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if (ret)
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dev_err(dev, "Unable to enable cores for TCM loading %d\n",
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ret);
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return ret;
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}
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static int k3_r5f_core_sanity_check(struct k3_r5f_core *core)
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{
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struct k3_r5f_cluster *cluster = core->cluster;
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if (core->in_use) {
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dev_err(dev, "Invalid op: Trying to load/start on already running core %d\n",
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core->tsp.proc_id);
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return -EINVAL;
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}
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !cluster->cores[1]) {
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printf("Secondary core is not probed in this cluster\n");
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return -EAGAIN;
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}
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP && !is_primary_core(core)) {
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dev_err(dev, "Invalid op: Trying to start secondary core %d in lockstep mode\n",
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core->tsp.proc_id);
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return -EINVAL;
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}
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if (cluster->mode == CLUSTER_MODE_SPLIT && !is_primary_core(core)) {
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if (!core->cluster->cores[0]->in_use) {
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dev_err(dev, "Invalid seq: Enable primary core before loading secondary core\n");
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return -EINVAL;
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}
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}
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return 0;
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}
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/* Zero out TCMs so that ECC can be effective on all TCM addresses */
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void k3_r5f_init_tcm_memories(struct k3_r5f_core *core, bool auto_inited)
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{
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if (core->ipdata->tcm_ecc_autoinit && auto_inited)
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return;
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if (core->atcm_enable)
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memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);
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if (core->btcm_enable)
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memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);
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}
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/**
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* k3_r5f_load() - Load up the Remote processor image
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* @dev: rproc device pointer
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* @addr: Address at which image is available
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* @size: size of the image
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*
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* Return: 0 if all goes good, else appropriate error message.
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*/
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static int k3_r5f_load(struct udevice *dev, ulong addr, ulong size)
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{
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struct k3_r5f_core *core = dev_get_priv(dev);
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u64 boot_vector;
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u32 ctrl, sts, cfg = 0;
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bool mem_auto_init;
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int ret;
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dev_dbg(dev, "%s addr = 0x%lx, size = 0x%lx\n", __func__, addr, size);
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ret = k3_r5f_core_sanity_check(core);
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if (ret)
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return ret;
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ret = k3_r5f_proc_request(core);
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if (ret)
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return ret;
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ret = ti_sci_proc_get_status(&core->tsp, &boot_vector, &cfg, &ctrl,
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&sts);
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if (ret)
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return ret;
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mem_auto_init = !(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
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ret = k3_r5f_prepare(dev);
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if (ret) {
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dev_err(dev, "R5f prepare failed for core %d\n",
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core->tsp.proc_id);
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goto proc_release;
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}
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k3_r5f_init_tcm_memories(core, mem_auto_init);
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ret = rproc_elf_load_image(dev, addr, size);
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if (ret < 0) {
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dev_err(dev, "Loading elf failedi %d\n", ret);
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goto proc_release;
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}
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boot_vector = rproc_elf_get_boot_addr(dev, addr);
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dev_dbg(dev, "%s: Boot vector = 0x%llx\n", __func__, boot_vector);
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ret = ti_sci_proc_set_config(&core->tsp, boot_vector, 0, 0);
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proc_release:
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k3_r5f_proc_release(core);
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return ret;
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}
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static int k3_r5f_core_halt(struct k3_r5f_core *core)
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{
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int ret;
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ret = ti_sci_proc_set_control(&core->tsp,
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PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
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if (ret)
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dev_err(core->dev, "Core %d failed to stop\n",
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core->tsp.proc_id);
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return ret;
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}
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static int k3_r5f_core_run(struct k3_r5f_core *core)
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{
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int ret;
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ret = ti_sci_proc_set_control(&core->tsp,
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0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
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if (ret) {
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dev_err(core->dev, "Core %d failed to start\n",
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core->tsp.proc_id);
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return ret;
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}
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return 0;
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}
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/**
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* k3_r5f_start() - Start the remote processor
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* @dev: rproc device pointer
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*
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* Return: 0 if all went ok, else return appropriate error
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*/
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static int k3_r5f_start(struct udevice *dev)
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{
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struct k3_r5f_core *core = dev_get_priv(dev);
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struct k3_r5f_cluster *cluster = core->cluster;
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int ret, c;
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dev_dbg(dev, "%s\n", __func__);
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ret = k3_r5f_core_sanity_check(core);
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if (ret)
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return ret;
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ret = k3_r5f_proc_request(core);
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if (ret)
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return ret;
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
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if (is_primary_core(core)) {
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for (c = NR_CORES - 1; c >= 0; c--) {
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ret = k3_r5f_core_run(cluster->cores[c]);
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if (ret)
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goto unroll_core_run;
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}
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} else {
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dev_err(dev, "Invalid op: Trying to start secondary core %d in lockstep mode\n",
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core->tsp.proc_id);
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ret = -EINVAL;
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goto proc_release;
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}
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} else {
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ret = k3_r5f_core_run(core);
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if (ret)
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goto proc_release;
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}
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core->in_use = true;
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k3_r5f_proc_release(core);
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return 0;
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unroll_core_run:
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while (c < NR_CORES) {
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k3_r5f_core_halt(cluster->cores[c]);
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c++;
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}
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proc_release:
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k3_r5f_proc_release(core);
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return ret;
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}
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static int k3_r5f_split_reset(struct k3_r5f_core *core)
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{
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int ret;
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dev_dbg(dev, "%s\n", __func__);
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if (reset_assert(&core->reset))
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ret = -EINVAL;
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if (ti_sci_proc_power_domain_off(&core->tsp))
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ret = -EINVAL;
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return ret;
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}
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static int k3_r5f_lockstep_reset(struct k3_r5f_cluster *cluster)
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{
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int ret = 0, c;
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dev_dbg(dev, "%s\n", __func__);
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for (c = 0; c < NR_CORES; c++)
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if (reset_assert(&cluster->cores[c]->reset))
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ret = -EINVAL;
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/* disable PSC modules on all applicable cores */
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for (c = 0; c < NR_CORES; c++)
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if (ti_sci_proc_power_domain_off(&cluster->cores[c]->tsp))
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ret = -EINVAL;
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return ret;
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}
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static int k3_r5f_unprepare(struct udevice *dev)
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{
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struct k3_r5f_core *core = dev_get_priv(dev);
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struct k3_r5f_cluster *cluster = core->cluster;
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int ret;
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dev_dbg(dev, "%s\n", __func__);
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if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
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if (is_primary_core(core))
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ret = k3_r5f_lockstep_reset(cluster);
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} else {
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ret = k3_r5f_split_reset(core);
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}
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if (ret)
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dev_warn(dev, "Unable to enable cores for TCM loading %d\n",
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ret);
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return 0;
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}
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static int k3_r5f_stop(struct udevice *dev)
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{
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struct k3_r5f_core *core = dev_get_priv(dev);
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struct k3_r5f_cluster *cluster = core->cluster;
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int c, ret;
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dev_dbg(dev, "%s\n", __func__);
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ret = k3_r5f_proc_request(core);
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if (ret)
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return ret;
|
|
|
|
core->in_use = false;
|
|
|
|
if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
|
|
if (is_primary_core(core)) {
|
|
for (c = 0; c < NR_CORES; c++)
|
|
k3_r5f_core_halt(cluster->cores[c]);
|
|
} else {
|
|
dev_err(dev, "Invalid op: Trying to stop secondary core in lockstep mode\n");
|
|
ret = -EINVAL;
|
|
goto proc_release;
|
|
}
|
|
} else {
|
|
k3_r5f_core_halt(core);
|
|
}
|
|
|
|
ret = k3_r5f_unprepare(dev);
|
|
proc_release:
|
|
k3_r5f_proc_release(core);
|
|
return ret;
|
|
}
|
|
|
|
static void *k3_r5f_da_to_va(struct udevice *dev, ulong da, ulong size)
|
|
{
|
|
struct k3_r5f_core *core = dev_get_priv(dev);
|
|
void __iomem *va = NULL;
|
|
phys_addr_t bus_addr;
|
|
u32 dev_addr, offset;
|
|
ulong mem_size;
|
|
int i;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
if (size <= 0)
|
|
return NULL;
|
|
|
|
for (i = 0; i < core->num_mems; i++) {
|
|
bus_addr = core->mem[i].bus_addr;
|
|
dev_addr = core->mem[i].dev_addr;
|
|
mem_size = core->mem[i].size;
|
|
|
|
if (da >= bus_addr && (da + size) <= (bus_addr + mem_size)) {
|
|
offset = da - bus_addr;
|
|
va = core->mem[i].cpu_addr + offset;
|
|
return (__force void *)va;
|
|
}
|
|
|
|
if (da >= dev_addr && (da + size) <= (dev_addr + mem_size)) {
|
|
offset = da - dev_addr;
|
|
va = core->mem[i].cpu_addr + offset;
|
|
return (__force void *)va;
|
|
}
|
|
}
|
|
|
|
/* Assume it is DDR region and return da */
|
|
return map_physmem(da, size, MAP_NOCACHE);
|
|
}
|
|
|
|
static int k3_r5f_init(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int k3_r5f_reset(struct udevice *dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_rproc_ops k3_r5f_rproc_ops = {
|
|
.init = k3_r5f_init,
|
|
.reset = k3_r5f_reset,
|
|
.start = k3_r5f_start,
|
|
.stop = k3_r5f_stop,
|
|
.load = k3_r5f_load,
|
|
.device_to_virt = k3_r5f_da_to_va,
|
|
};
|
|
|
|
static int k3_r5f_rproc_configure(struct k3_r5f_core *core)
|
|
{
|
|
struct k3_r5f_cluster *cluster = core->cluster;
|
|
u32 set_cfg = 0, clr_cfg = 0, cfg, ctrl, sts;
|
|
bool lockstep_permitted;
|
|
u64 boot_vec = 0;
|
|
int ret;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
ret = ti_sci_proc_request(&core->tsp);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* Do not touch boot vector now. Load will take care of it. */
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_GEN_IGN_BOOTVECTOR;
|
|
|
|
ret = ti_sci_proc_get_status(&core->tsp, &boot_vec, &cfg, &ctrl, &sts);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* Sanity check for Lockstep mode */
|
|
lockstep_permitted = !!(sts &
|
|
PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
|
|
if (cluster->mode && is_primary_core(core) && !lockstep_permitted) {
|
|
dev_err(core->dev, "LockStep mode not permitted on this device\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Primary core only configuration */
|
|
if (is_primary_core(core)) {
|
|
/* always enable ARM mode */
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TEINIT;
|
|
if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
|
|
set_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
|
|
else if (lockstep_permitted)
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
|
|
}
|
|
|
|
if (core->atcm_enable)
|
|
set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
|
|
else
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
|
|
|
|
if (core->btcm_enable)
|
|
set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
|
|
else
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
|
|
|
|
if (core->loczrama)
|
|
set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
|
|
else
|
|
clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
|
|
|
|
ret = k3_r5f_core_halt(core);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = ti_sci_proc_set_config(&core->tsp, boot_vec, set_cfg, clr_cfg);
|
|
out:
|
|
ti_sci_proc_release(&core->tsp);
|
|
return ret;
|
|
}
|
|
|
|
static int ti_sci_proc_of_to_priv(struct udevice *dev, struct ti_sci_proc *tsp)
|
|
{
|
|
u32 ids[2];
|
|
int ret;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
tsp->sci = ti_sci_get_by_phandle(dev, "ti,sci");
|
|
if (IS_ERR(tsp->sci)) {
|
|
dev_err(dev, "ti_sci get failed: %ld\n", PTR_ERR(tsp->sci));
|
|
return PTR_ERR(tsp->sci);
|
|
}
|
|
|
|
ret = dev_read_u32_array(dev, "ti,sci-proc-ids", ids, 2);
|
|
if (ret) {
|
|
dev_err(dev, "Proc IDs not populated %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
tsp->ops = &tsp->sci->ops.proc_ops;
|
|
tsp->proc_id = ids[0];
|
|
tsp->host_id = ids[1];
|
|
tsp->dev_id = dev_read_u32_default(dev, "ti,sci-dev-id",
|
|
TI_SCI_RESOURCE_NULL);
|
|
if (tsp->dev_id == TI_SCI_RESOURCE_NULL) {
|
|
dev_err(dev, "Device ID not populated %d\n", ret);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int k3_r5f_of_to_priv(struct k3_r5f_core *core)
|
|
{
|
|
int ret;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
core->atcm_enable = dev_read_u32_default(core->dev, "atcm-enable", 0);
|
|
core->btcm_enable = dev_read_u32_default(core->dev, "btcm-enable", 1);
|
|
core->loczrama = dev_read_u32_default(core->dev, "loczrama", 1);
|
|
|
|
ret = ti_sci_proc_of_to_priv(core->dev, &core->tsp);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = reset_get_by_index(core->dev, 0, &core->reset);
|
|
if (ret) {
|
|
dev_err(core->dev, "Reset lines not available: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
core->ipdata = (struct k3_r5f_ip_data *)dev_get_driver_data(core->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int k3_r5f_core_of_get_memories(struct k3_r5f_core *core)
|
|
{
|
|
static const char * const mem_names[] = {"atcm", "btcm"};
|
|
struct udevice *dev = core->dev;
|
|
int i;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
core->num_mems = ARRAY_SIZE(mem_names);
|
|
core->mem = calloc(core->num_mems, sizeof(*core->mem));
|
|
if (!core->mem)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < core->num_mems; i++) {
|
|
core->mem[i].bus_addr = dev_read_addr_size_name(dev,
|
|
mem_names[i],
|
|
(fdt_addr_t *)&core->mem[i].size);
|
|
if (core->mem[i].bus_addr == FDT_ADDR_T_NONE) {
|
|
dev_err(dev, "%s bus address not found\n",
|
|
mem_names[i]);
|
|
return -EINVAL;
|
|
}
|
|
core->mem[i].cpu_addr = map_physmem(core->mem[i].bus_addr,
|
|
core->mem[i].size,
|
|
MAP_NOCACHE);
|
|
if (!strcmp(mem_names[i], "atcm")) {
|
|
core->mem[i].dev_addr = core->loczrama ?
|
|
0 : K3_R5_TCM_DEV_ADDR;
|
|
} else {
|
|
core->mem[i].dev_addr = core->loczrama ?
|
|
K3_R5_TCM_DEV_ADDR : 0;
|
|
}
|
|
|
|
dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
|
|
mem_names[i], &core->mem[i].bus_addr,
|
|
core->mem[i].size, core->mem[i].cpu_addr,
|
|
core->mem[i].dev_addr);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
|
|
* split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
|
|
* cores are usable in Split-mode, but only the Core0 TCMs can be used in
|
|
* LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
|
|
* leveraging the Core1 TCMs as well in certain modes where they would have
|
|
* otherwise been unusable (Eg: LockStep-mode on J7200 SoCs). This is done by
|
|
* making a Core1 TCM visible immediately after the corresponding Core0 TCM.
|
|
* The SoC memory map uses the larger 64 KB sizes for the Core0 TCMs, and the
|
|
* dts representation reflects this increased size on supported SoCs. The Core0
|
|
* TCM sizes therefore have to be adjusted to only half the original size in
|
|
* Split mode.
|
|
*/
|
|
static void k3_r5f_core_adjust_tcm_sizes(struct k3_r5f_core *core)
|
|
{
|
|
struct k3_r5f_cluster *cluster = core->cluster;
|
|
|
|
if (cluster->mode == CLUSTER_MODE_LOCKSTEP)
|
|
return;
|
|
|
|
if (!core->ipdata->tcm_is_double)
|
|
return;
|
|
|
|
if (core == cluster->cores[0]) {
|
|
core->mem[0].size /= 2;
|
|
core->mem[1].size /= 2;
|
|
|
|
dev_dbg(core->dev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
|
|
core->mem[0].size, core->mem[1].size);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* k3_r5f_probe() - Basic probe
|
|
* @dev: corresponding k3 remote processor device
|
|
*
|
|
* Return: 0 if all goes good, else appropriate error message.
|
|
*/
|
|
static int k3_r5f_probe(struct udevice *dev)
|
|
{
|
|
struct k3_r5f_cluster *cluster = dev_get_priv(dev->parent);
|
|
struct k3_r5f_core *core = dev_get_priv(dev);
|
|
bool r_state;
|
|
int ret;
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
core->dev = dev;
|
|
ret = k3_r5f_of_to_priv(core);
|
|
if (ret)
|
|
return ret;
|
|
|
|
core->cluster = cluster;
|
|
/* Assume Primary core gets probed first */
|
|
if (!cluster->cores[0])
|
|
cluster->cores[0] = core;
|
|
else
|
|
cluster->cores[1] = core;
|
|
|
|
ret = k3_r5f_core_of_get_memories(core);
|
|
if (ret) {
|
|
dev_err(dev, "Rproc getting internal memories failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
|
|
&r_state, &core->in_use);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (core->in_use) {
|
|
dev_info(dev, "Core %d is already in use. No rproc commands work\n",
|
|
core->tsp.proc_id);
|
|
return 0;
|
|
}
|
|
|
|
/* Make sure Local reset is asserted. Redundant? */
|
|
reset_assert(&core->reset);
|
|
|
|
ret = k3_r5f_rproc_configure(core);
|
|
if (ret) {
|
|
dev_err(dev, "rproc configure failed %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
k3_r5f_core_adjust_tcm_sizes(core);
|
|
|
|
dev_dbg(dev, "Remoteproc successfully probed\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int k3_r5f_remove(struct udevice *dev)
|
|
{
|
|
struct k3_r5f_core *core = dev_get_priv(dev);
|
|
|
|
free(core->mem);
|
|
|
|
ti_sci_proc_release(&core->tsp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct k3_r5f_ip_data k3_data = {
|
|
.tcm_is_double = false,
|
|
.tcm_ecc_autoinit = false,
|
|
};
|
|
|
|
static const struct k3_r5f_ip_data j7200_data = {
|
|
.tcm_is_double = true,
|
|
.tcm_ecc_autoinit = true,
|
|
};
|
|
|
|
static const struct udevice_id k3_r5f_rproc_ids[] = {
|
|
{ .compatible = "ti,am654-r5f", .data = (ulong)&k3_data, },
|
|
{ .compatible = "ti,j721e-r5f", .data = (ulong)&k3_data, },
|
|
{ .compatible = "ti,j7200-r5f", .data = (ulong)&j7200_data, },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(k3_r5f_rproc) = {
|
|
.name = "k3_r5f_rproc",
|
|
.of_match = k3_r5f_rproc_ids,
|
|
.id = UCLASS_REMOTEPROC,
|
|
.ops = &k3_r5f_rproc_ops,
|
|
.probe = k3_r5f_probe,
|
|
.remove = k3_r5f_remove,
|
|
.priv_auto_alloc_size = sizeof(struct k3_r5f_core),
|
|
};
|
|
|
|
static int k3_r5f_cluster_probe(struct udevice *dev)
|
|
{
|
|
struct k3_r5f_cluster *cluster = dev_get_priv(dev);
|
|
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
|
|
cluster->mode = dev_read_u32_default(dev, "lockstep-mode",
|
|
CLUSTER_MODE_LOCKSTEP);
|
|
|
|
if (device_get_child_count(dev) != 2) {
|
|
dev_err(dev, "Invalid number of R5 cores");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev_dbg(dev, "%s: Cluster successfully probed in %s mode\n",
|
|
__func__, cluster->mode ? "lockstep" : "split");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id k3_r5fss_ids[] = {
|
|
{ .compatible = "ti,am654-r5fss"},
|
|
{ .compatible = "ti,j721e-r5fss"},
|
|
{ .compatible = "ti,j7200-r5fss"},
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(k3_r5fss) = {
|
|
.name = "k3_r5fss",
|
|
.of_match = k3_r5fss_ids,
|
|
.id = UCLASS_MISC,
|
|
.probe = k3_r5f_cluster_probe,
|
|
.priv_auto_alloc_size = sizeof(struct k3_r5f_cluster),
|
|
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
|
|
};
|