mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 18:41:03 +00:00
a8c281d4b7
This converts the following to Kconfig: CONFIG_REMAKE_ELF Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
142 lines
4.3 KiB
C
142 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2018 congatec AG
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*
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*/
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#ifndef __CGTQMX8_H
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#define __CGTQMX8_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_MAX_SIZE (124 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
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#define CONFIG_SPL_STACK 0x013E000
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#define CONFIG_SPL_BSS_START_ADDR 0x00128000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
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#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
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#define CONFIG_MALLOC_F_ADDR 0x00120000
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#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif
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/* Flat Device Tree Definitions */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define USDHC1_BASE_ADDR 0x5B010000
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#define USDHC2_BASE_ADDR 0x5B020000
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#define USDHC3_BASE_ADDR 0x5B030000
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/* Boot M4 */
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#define M4_BOOT_ENV \
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"m4_0_image=m4_0.bin\0" \
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"m4_1_image=m4_1.bin\0" \
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"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
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"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
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"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
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"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
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#ifdef CONFIG_NAND_BOOT
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#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
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#else
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#define MFG_NAND_PARTITION ""
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#endif
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#define FEC0_RESET IMX_GPIO_NR(2, 5)
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#define FEC0_PDOMAIN "conn_enet0"
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#define CONFIG_MFG_ENV_SETTINGS \
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"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
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"rdinit=/linuxrc " \
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"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
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"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
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"g_mass_storage.iSerialNumber=\"\" "\
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MFG_NAND_PARTITION \
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"clk_ignore_unused "\
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"\0" \
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"initrd_addr=0x83800000\0" \
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"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_MFG_ENV_SETTINGS \
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M4_BOOT_ENV \
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"script=boot.scr\0" \
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"image=Image\0" \
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"panel=NULL\0" \
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"console=ttyLP0\0" \
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"fdt_addr=0x83000000\0" \
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"boot_fdt=try\0" \
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"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"echo wait for boot; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console},${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"booti; " \
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"fi;\0"
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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#define PHYS_SDRAM_2 0x880000000
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#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
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#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 8000000 /* 8MHz */
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/* Networking */
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#define CONFIG_FEC_MXC_PHYADDR -1
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define FEC_QUIRK_ENET_MAC
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#endif /* __CGTQMX8_H */
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