mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
151 lines
4.2 KiB
C
151 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018 NXP
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*/
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#ifndef __LS1088_COMMON_H
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#define __LS1088_COMMON_H
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/* SPL build */
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#ifdef CONFIG_SPL_BUILD
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#define SPL_NO_BOARDINFO
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#define SPL_NO_QIXIS
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#define SPL_NO_PCI
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#define SPL_NO_ENV
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#define SPL_NO_RTC
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#define SPL_NO_USB
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#define SPL_NO_SATA
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#define SPL_NO_QSPI
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#define SPL_NO_IFC
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#endif
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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#define LS1088ARDB_PB_BOARD 0x4A
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/* Link Definitions */
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/* Link Definitions */
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#define CFG_SYS_FSL_QSPI_BASE 0x20000000
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#define CONFIG_VERY_BIG_RAM
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#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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#define CFG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
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/*
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* SMP Definitinos
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*/
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#define CPU_RELEASE_ADDR secondary_boot_addr
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/* GPIO */
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/* I2C */
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/* Serial Port */
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#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
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/*
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* During booting, IFC is mapped at the region of 0x30000000.
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* But this region is limited to 256MB. To accommodate NOR, promjet
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* and FPGA. This region is divided as below:
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* 0x30000000 - 0x37ffffff : 128MB : NOR flash
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* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
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* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
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*
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* To accommodate bigger NOR flash and other devices, we will map IFC
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* chip selects to as below:
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* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
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* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
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* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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*
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* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
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* CFG_SYS_FLASH_BASE has the final address (core view)
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* CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_TEXT_BASE is linked to 0x30000000 for booting
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*/
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#define CFG_SYS_FLASH_BASE 0x580000000ULL
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#define CFG_SYS_FLASH_BASE_PHYS 0x80000000
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#define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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#define CFG_SYS_FLASH1_BASE_PHYS 0xC0000000
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#define CFG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
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#ifndef __ASSEMBLY__
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unsigned long long get_qixis_addr(void);
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#endif
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#define QIXIS_BASE get_qixis_addr()
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#define QIXIS_BASE_PHYS 0x20000000
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#define QIXIS_BASE_PHYS_EARLY 0xC000000
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#define CFG_SYS_NAND_BASE 0x530000000ULL
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#define CFG_SYS_NAND_BASE_PHYS 0x30000000
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/* MC firmware */
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/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
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#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
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#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
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#define CFG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
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#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
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#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
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#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
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/*
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* Carve out a DDR region which will not be used by u-boot/Linux
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*
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* It will be used by MC and Debug Server. The MC region must be
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* 512MB aligned, so the min size to hide is 512MB.
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*/
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#if defined(CONFIG_FSL_MC_ENET)
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#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
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#endif
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/* Miscellaneous configurable options */
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/* Physical Memory Map */
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#ifndef SPL_NO_ENV
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyAMA0,38400n8\0" \
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"mcinitcmd=fsl_mc start mc 0x580a00000" \
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" 0x580e00000 \0"
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#endif
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#ifdef CONFIG_SPL
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#ifdef CONFIG_NXP_ESBC
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw u-boot image instead of fit image.
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*/
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#endif /* ifdef CONFIG_NXP_ESBC */
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#endif
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#endif /* __LS1088_COMMON_H */
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