mirror of
https://github.com/AsahiLinux/u-boot
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0d13a0051b
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
NOTE: This change is useless until we get proper SPL support, at
which point this will likely need further rework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pavel Machek <pavel@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Vince Bridgers <vbridger@opensource.altera.com>
109 lines
3.7 KiB
C
109 lines
3.7 KiB
C
/*
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* Copyright Altera Corporation (C) 2012-2014. All rights reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* This file is generated by Preloader Generator */
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#ifndef _PRELOADER_PLL_CONFIG_H_
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#define _PRELOADER_PLL_CONFIG_H_
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/* PLL configuration data */
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/* Main PLL */
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#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
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#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
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#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
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/*
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* To tell where is the clock source:
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* 0 = MAINPLL
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* 1 = PERIPHPLL
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*/
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
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/* Peripheral PLL */
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#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
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#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (39)
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/*
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* To tell where is the VCOs source:
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* 0 = EOSC1
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* 1 = EOSC2
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* 2 = F2S
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*/
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#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
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#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
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#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)
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#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
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#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)
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#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
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#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
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#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
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/*
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* To tell where is the clock source:
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* 0 = F2S_PERIPH_REF_CLK
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* 1 = MAIN_CLK
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* 2 = PERIPH_CLK
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*/
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#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)
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#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
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#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
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/* SDRAM PLL */
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#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
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#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
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/*
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* To tell where is the VCOs source:
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* 0 = EOSC1
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* 1 = EOSC2
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* 2 = F2S
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*/
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#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
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/* Info for driver */
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#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
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#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
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#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
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#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
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#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
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#define CONFIG_HPS_CLK_EMAC0_HZ (250000000)
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#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
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#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
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#define CONFIG_HPS_CLK_NAND_HZ (50000000)
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#define CONFIG_HPS_CLK_SDMMC_HZ (200000000)
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#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
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#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
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#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
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#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
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#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
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#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
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#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
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#endif /* _PRELOADER_PLL_CONFIG_H_ */
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