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base_addr_a10.h
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arm: socfpga: Add A10 macros
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2017-05-18 11:33:17 +02:00 |
base_addr_ac5.h
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ARM: socfpga: rename the cyclone5 and arria5 base address file
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2015-11-30 13:30:19 +01:00 |
boot0.h
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ARM: socfpga: boot0 hook: remove macro from boot0 header file
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2017-04-14 14:06:42 +02:00 |
clock_manager.h
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arm: socfpga: Add clock driver for Arria 10
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2017-05-18 11:33:17 +02:00 |
clock_manager_arria10.h
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arm: socfpga: Add clock driver for Arria 10
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2017-05-18 11:33:17 +02:00 |
clock_manager_gen5.h
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arm: socfpga: Restructure clock manager driver
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2017-05-18 11:33:16 +02:00 |
fpga_manager.h
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arm: socfpga: Add FPGA driver support for Arria 10
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2017-07-26 10:31:44 +02:00 |
fpga_manager_arria10.h
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arm: socfpga: Add FPGA driver support for Arria 10
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2017-07-26 10:31:44 +02:00 |
fpga_manager_gen5.h
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arm: socfpga: Restructure FPGA driver in the preparation to support A10
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2017-07-26 10:31:44 +02:00 |
freeze_controller.h
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gpio.h
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misc.h
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arm: socfpga: Add misc support for Arria 10
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2017-05-18 11:33:18 +02:00 |
nic301.h
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pinmux.h
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arm: socfpga: Add pinmux for Arria 10
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2017-05-18 11:33:18 +02:00 |
reset_manager.h
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arm: socfpga: Add reset driver support for Arria 10
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2017-05-18 11:33:17 +02:00 |
reset_manager_arria10.h
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arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
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2017-07-26 10:31:43 +02:00 |
reset_manager_gen5.h
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arm: socfpga: Restructure reset manager driver
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2017-05-18 11:33:17 +02:00 |
scan_manager.h
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arm: socfpga: scan: Add code to get FPGA ID
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2015-08-08 14:14:30 +02:00 |
scu.h
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sdram.h
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ddr: altera: Configuring SDRAM extra cycles timing parameters
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2016-10-27 08:03:07 +02:00 |
sdram_arria10.h
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arm: socfpga: Add sdram header file for Arria 10
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2017-05-18 11:33:18 +02:00 |
system_manager.h
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arm: socfpga: Add system manager for Arria 10
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2017-05-18 11:33:18 +02:00 |
system_manager_arria10.h
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arm: socfpga: Add system manager for Arria 10
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2017-05-18 11:33:18 +02:00 |
system_manager_gen5.h
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arm: socfpga: Restructure system manager
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2017-05-18 11:33:17 +02:00 |
timer.h
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