mirror of
https://github.com/AsahiLinux/u-boot
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8dd0dff269
The Ethernet has been broken for some time. This patch unifies this board with a few others that use a similar approach to enabling phy. This fixes ar8031 Ethernet controller so it works. Signed-off-by: Adam Ford <aford173@gmail.com>
368 lines
10 KiB
C
368 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Logic PD, Inc.
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*
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* Author: Adam Ford <aford173@gmail.com>
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*
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* Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
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* and updates by Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <input.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart2_pads[] = {
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MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart3_pads[] = {
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MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
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}
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static iomux_v3_cfg_t const nand_pads[] = {
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MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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};
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static void setup_nand_pins(void)
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{
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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/* To enable AR8031 output a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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val &= 0xffe3;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_nand_pins();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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env_set("board_name", "imx6logic");
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if (is_mx6dq()) {
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env_set("board_rev", "MX6DQ");
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env_set("fdt_file", "imx6q-logicpd.dtb");
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}
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6q-ddr.h>
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#include <spl.h>
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#include <linux/libfdt.h>
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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/* SD interface */
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#define USDHC_PAD_CTRL \
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(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
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};
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg usdhc_cfg[] = {
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{USDHC1_BASE_ADDR}, /* SOM */
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{USDHC2_BASE_ADDR} /* Baseboard */
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};
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int board_mmc_init(bd_t *bis)
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{
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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unsigned int reg = readl(&psrc->sbmr1) >> 11;
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/*
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* Upon reading BOOT_CFG register the following map is done:
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* Bit 11 and 12 of BOOT_CFG register can determine the current
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* mmc port
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* 0x1 SD1-SOM
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* 0x2 SD2-Baseboard
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*/
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reg &= 0x3; /* Only care about bottom 2 bits */
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switch (reg) {
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case 0:
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SETUP_IOMUX_PADS(usdhc1_pads);
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usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
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break;
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case 1:
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SETUP_IOMUX_PADS(usdhc2_pads);
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usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
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break;
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}
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return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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#endif
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0xFFFFF300, &ccm->CCGR4);
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writel(0x0F0000F3, &ccm->CCGR5);
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writel(0x00000FFF, &ccm->CCGR6);
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}
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static int mx6q_dcd_table[] = {
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MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
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MX6_IOM_GRP_DDRPKE, 0x00000000,
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MX6_IOM_DRAM_SDCLK_0, 0x00000030,
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MX6_IOM_DRAM_SDCLK_1, 0x00000030,
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MX6_IOM_DRAM_CAS, 0x00000030,
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MX6_IOM_DRAM_RAS, 0x00000030,
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MX6_IOM_GRP_ADDDS, 0x00000030,
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MX6_IOM_DRAM_RESET, 0x00000030,
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MX6_IOM_DRAM_SDBA2, 0x00000000,
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MX6_IOM_DRAM_SDODT0, 0x00000030,
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MX6_IOM_DRAM_SDODT1, 0x00000030,
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MX6_IOM_GRP_CTLDS, 0x00000030,
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MX6_IOM_DDRMODE_CTL, 0x00020000,
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MX6_IOM_DRAM_SDQS0, 0x00000030,
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MX6_IOM_DRAM_SDQS1, 0x00000030,
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MX6_IOM_DRAM_SDQS2, 0x00000030,
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MX6_IOM_DRAM_SDQS3, 0x00000030,
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MX6_IOM_GRP_DDRMODE, 0x00020000,
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MX6_IOM_GRP_B0DS, 0x00000030,
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MX6_IOM_GRP_B1DS, 0x00000030,
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MX6_IOM_GRP_B2DS, 0x00000030,
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MX6_IOM_GRP_B3DS, 0x00000030,
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MX6_IOM_DRAM_DQM0, 0x00000030,
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MX6_IOM_DRAM_DQM1, 0x00000030,
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MX6_IOM_DRAM_DQM2, 0x00000030,
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MX6_IOM_DRAM_DQM3, 0x00000030,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
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MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
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MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
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MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
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MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
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MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
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MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
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MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
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MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
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MX6_MMDC_P0_MPMUR0, 0x00000800,
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MX6_MMDC_P0_MDPDC, 0x00020036,
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MX6_MMDC_P0_MDOTC, 0x09444040,
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MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
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MX6_MMDC_P0_MDCFG1, 0xFF328F64,
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MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
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MX6_MMDC_P0_MDMISC, 0x00011740,
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MX6_MMDC_P0_MDSCR, 0x00008000,
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MX6_MMDC_P0_MDRWD, 0x000026D2,
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MX6_MMDC_P0_MDOR, 0x00BE1023,
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MX6_MMDC_P0_MDASP, 0x00000047,
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MX6_MMDC_P0_MDCTL, 0x85190000,
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MX6_MMDC_P0_MDSCR, 0x00888032,
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MX6_MMDC_P0_MDSCR, 0x00008033,
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MX6_MMDC_P0_MDSCR, 0x00008031,
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MX6_MMDC_P0_MDSCR, 0x19408030,
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MX6_MMDC_P0_MDSCR, 0x04008040,
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MX6_MMDC_P0_MDREF, 0x00007800,
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MX6_MMDC_P0_MPODTCTRL, 0x00000007,
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MX6_MMDC_P0_MDPDC, 0x00025576,
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MX6_MMDC_P0_MAPSR, 0x00011006,
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MX6_MMDC_P0_MDSCR, 0x00000000,
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/* enable AXI cache for VDOA/VPU/IPU */
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MX6_IOMUXC_GPR4, 0xF00000CF,
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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MX6_IOMUXC_GPR6, 0x007F007F,
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MX6_IOMUXC_GPR7, 0x007F007F,
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};
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static void ddr_init(int *table, int size)
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{
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int i;
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for (i = 0; i < size / 2 ; i++)
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writel(table[2 * i + 1], table[2 * i]);
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}
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static void spl_dram_init(void)
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{
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if (is_mx6dq())
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ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
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}
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void board_init_f(ulong dummy)
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{
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/* DDR initialization */
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spl_dram_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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ccgr_init();
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gpr_init();
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/* iomux and setup of uart and NAND pins */
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board_early_init_f();
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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/* load/boot image from boot device */
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board_init_r(NULL, 0);
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}
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#endif
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