mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
68d5342017
There are already Kconfig options for SPI flash drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
167 lines
4.8 KiB
C
167 lines
4.8 KiB
C
/*
|
|
* Copyright (C) 2014 Stefan Roese <sr@denx.de>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _CONFIG_DB_MV7846MP_GP_H
|
|
#define _CONFIG_DB_MV7846MP_GP_H
|
|
|
|
/*
|
|
* High Level Configuration Options (easy to change)
|
|
*/
|
|
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
|
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
|
#endif
|
|
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
|
|
|
/*
|
|
* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
|
|
* for DDR ECC byte filling in the SPL before loading the main
|
|
* U-Boot into it.
|
|
*/
|
|
#define CONFIG_SYS_TEXT_BASE 0x00800000
|
|
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
|
|
|
|
/*
|
|
* Commands configuration
|
|
*/
|
|
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
|
|
#define CONFIG_CMD_DHCP
|
|
#define CONFIG_CMD_ENV
|
|
#define CONFIG_CMD_I2C
|
|
#define CONFIG_CMD_IDE
|
|
#define CONFIG_CMD_NAND
|
|
#define CONFIG_CMD_PCI
|
|
#define CONFIG_CMD_PING
|
|
#define CONFIG_CMD_SF
|
|
#define CONFIG_CMD_SPI
|
|
#define CONFIG_CMD_TFTPPUT
|
|
#define CONFIG_CMD_TIME
|
|
|
|
/* I2C */
|
|
#define CONFIG_SYS_I2C
|
|
#define CONFIG_SYS_I2C_MVTWSI
|
|
#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
|
|
#define CONFIG_SYS_I2C_SLAVE 0x0
|
|
#define CONFIG_SYS_I2C_SPEED 100000
|
|
|
|
/* USB/EHCI configuration */
|
|
#define CONFIG_EHCI_IS_TDI
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
|
|
|
/* SPI NOR flash default params, used by sf commands */
|
|
#define CONFIG_SF_DEFAULT_SPEED 1000000
|
|
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
|
|
|
|
/* Environment in SPI NOR flash */
|
|
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
|
#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
|
|
#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
|
|
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
|
|
|
|
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
|
|
#define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 }
|
|
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII
|
|
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
|
#define CONFIG_RESET_PHY_R
|
|
|
|
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
|
|
#define CONFIG_SYS_ALT_MEMTEST
|
|
|
|
/* SATA support */
|
|
#ifdef CONFIG_CMD_IDE
|
|
#define __io
|
|
#define CONFIG_IDE_PREINIT
|
|
#define CONFIG_MVSATA_IDE
|
|
|
|
/* Needs byte-swapping for ATA data register */
|
|
#define CONFIG_IDE_SWAP_IO
|
|
|
|
#define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */
|
|
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */
|
|
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
|
|
|
|
/* Each 8-bit ATA register is aligned to a 4-bytes address */
|
|
#define CONFIG_SYS_ATA_STRIDE 4
|
|
|
|
/* CONFIG_CMD_IDE requires some #defines for ATA registers */
|
|
#define CONFIG_SYS_IDE_MAXBUS 2
|
|
#define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS
|
|
|
|
/* ATA registers base is at SATA controller base */
|
|
#define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE
|
|
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000
|
|
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000
|
|
|
|
#define CONFIG_DOS_PARTITION
|
|
#endif /* CONFIG_CMD_IDE */
|
|
|
|
/* PCIe support */
|
|
#define CONFIG_PCI
|
|
#define CONFIG_PCI_MVEBU
|
|
#define CONFIG_PCI_PNP
|
|
#define CONFIG_PCI_SCAN_SHOW
|
|
#define CONFIG_E1000 /* enable Intel E1000 support for testing */
|
|
|
|
/* NAND */
|
|
#define CONFIG_SYS_NAND_USE_FLASH_BBT
|
|
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
|
|
|
/*
|
|
* mv-common.h should be defined after CMD configs since it used them
|
|
* to enable certain macros
|
|
*/
|
|
#include "mv-common.h"
|
|
|
|
/*
|
|
* Memory layout while starting into the bin_hdr via the
|
|
* BootROM:
|
|
*
|
|
* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
|
|
* 0x4000.4030 bin_hdr start address
|
|
* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
|
|
* 0x4007.fffc BootROM stack top
|
|
*
|
|
* The address space between 0x4007.fffc and 0x400f.fff is not locked in
|
|
* L2 cache thus cannot be used.
|
|
*/
|
|
|
|
/* SPL */
|
|
/* Defines for SPL */
|
|
#define CONFIG_SPL_FRAMEWORK
|
|
#define CONFIG_SPL_TEXT_BASE 0x40004030
|
|
#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
|
|
|
|
#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
|
|
#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
|
|
|
|
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
|
|
CONFIG_SPL_BSS_MAX_SIZE)
|
|
#define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10)
|
|
|
|
#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
|
|
#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
|
|
|
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
|
#define CONFIG_SPL_I2C_SUPPORT
|
|
|
|
/* SPL related SPI defines */
|
|
#define CONFIG_SPL_SPI_SUPPORT
|
|
#define CONFIG_SPL_SPI_FLASH_SUPPORT
|
|
#define CONFIG_SPL_SPI_LOAD
|
|
#define CONFIG_SPL_SPI_BUS 0
|
|
#define CONFIG_SPL_SPI_CS 0
|
|
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
|
|
#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
|
|
|
|
/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
|
|
#define CONFIG_SYS_MVEBU_DDR_AXP
|
|
#define CONFIG_SPD_EEPROM 0x4e
|
|
|
|
#endif /* _CONFIG_DB_MV7846MP_GP_H */
|