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5ed3e8659e
Add common clock, memory and low level code Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
381 lines
12 KiB
C
381 lines
12 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Manikandan Pillai <mani.pillai@ti.com>
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*
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* Derived from Beagle Board and OMAP3 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clocks.h>
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#include <asm/arch/clocks_omap3.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/sys_proto.h>
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#include <environment.h>
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#include <command.h>
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/******************************************************************************
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* get_sys_clk_speed() - determine reference oscillator speed
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* based on known 32kHz clock and gptimer.
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*****************************************************************************/
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u32 get_osc_clk_speed(void)
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{
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u32 start, cstart, cend, cdiff, val;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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prm_t *prm_base = (prm_t *)PRM_BASE;
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gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
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s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
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val = readl(&prm_base->clksrc_ctrl);
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/* If SYS_CLK is being divided by 2, remove for now */
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val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
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writel(val, &prm_base->clksrc_ctrl);
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/* enable timer2 */
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val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
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/* select sys_clk for GPT1 */
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writel(val, &prcm_base->clksel_wkup);
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/* Enable I and F Clocks for GPT1 */
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val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
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writel(val, &prcm_base->iclken_wkup);
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val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
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writel(val, &prcm_base->fclken_wkup);
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writel(0, &gpt1_base->tldr); /* start counting at 0 */
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writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
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/* enable 32kHz source, determine sys_clk via gauging */
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/* start time in 20 cycles */
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start = 20 + readl(&s32k_base->s32k_cr);
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/* dead loop till start time */
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while (readl(&s32k_base->s32k_cr) < start);
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/* get start sys_clk count */
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cstart = readl(&gpt1_base->tcrr);
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/* wait for 40 cycles */
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while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
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cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
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cdiff = cend - cstart; /* get elapsed ticks */
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/* based on number of ticks assign speed */
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if (cdiff > 19000)
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return S38_4M;
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else if (cdiff > 15200)
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return S26M;
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else if (cdiff > 13000)
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return S24M;
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else if (cdiff > 9000)
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return S19_2M;
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else if (cdiff > 7600)
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return S13M;
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else
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return S12M;
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}
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/******************************************************************************
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* get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
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* input oscillator clock frequency.
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*****************************************************************************/
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void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
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{
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switch(osc_clk) {
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case S38_4M:
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*sys_clkin_sel = 4;
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break;
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case S26M:
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*sys_clkin_sel = 3;
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break;
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case S19_2M:
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*sys_clkin_sel = 2;
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break;
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case S13M:
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*sys_clkin_sel = 1;
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break;
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case S12M:
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default:
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*sys_clkin_sel = 0;
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}
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}
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/******************************************************************************
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* prcm_init() - inits clocks for PRCM as defined in clocks.h
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* called from SRAM, or Flash (using temp SRAM stack).
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*****************************************************************************/
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void prcm_init(void)
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{
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void (*f_lock_pll) (u32, u32, u32, u32);
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int xip_safe, p0, p1, p2, p3;
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u32 osc_clk = 0, sys_clkin_sel;
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u32 clk_index, sil_index;
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prm_t *prm_base = (prm_t *)PRM_BASE;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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dpll_param *dpll_param_p;
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f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
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SRAM_VECT_CODE);
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xip_safe = is_running_in_sram();
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/*
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* Gauge the input clock speed and find out the sys_clkin_sel
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* value corresponding to the input clock.
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*/
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osc_clk = get_osc_clk_speed();
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get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
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/* set input crystal speed */
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sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
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/* If the input clock is greater than 19.2M always divide/2 */
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if (sys_clkin_sel > 2) {
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/* input clock divider */
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sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
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clk_index = sys_clkin_sel / 2;
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} else {
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/* input clock divider */
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sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
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clk_index = sys_clkin_sel;
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}
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/*
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* The DPLL tables are defined according to sysclk value and
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* silicon revision. The clk_index value will be used to get
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* the values for that input sysclk from the DPLL param table
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* and sil_index will get the values for that SysClk for the
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* appropriate silicon rev.
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*/
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sil_index = get_cpu_rev() - 1;
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/* Unlock MPU DPLL (slows things down, and needed later) */
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sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
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wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY);
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/* Getting the base address of Core DPLL param table */
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dpll_param_p = (dpll_param *) get_core_dpll_param();
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/* Moving it to the right sysclk and ES rev base */
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dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
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if (xip_safe) {
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/*
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* CORE DPLL
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* sr32(CM_CLKSEL2_EMU) set override to work when asleep
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*/
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sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
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wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
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LDELAY);
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/*
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* For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
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* work. write another value and then default value.
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*/
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/* m3x2 */
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sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2 + 1);
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/* m3x2 */
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sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
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/* Set M2 */
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sr32(&prcm_base->clksel1_pll, 27, 2, dpll_param_p->m2);
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/* Set M */
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sr32(&prcm_base->clksel1_pll, 16, 11, dpll_param_p->m);
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/* Set N */
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sr32(&prcm_base->clksel1_pll, 8, 7, dpll_param_p->n);
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/* 96M Src */
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sr32(&prcm_base->clksel1_pll, 6, 1, 0);
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/* ssi */
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sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
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/* fsusb */
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sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
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/* l4 */
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sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
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/* l3 */
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sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
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/* gfx */
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sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
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/* reset mgr */
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sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
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/* FREQSEL */
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sr32(&prcm_base->clken_pll, 4, 4, dpll_param_p->fsel);
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/* lock mode */
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sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
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wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
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LDELAY);
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} else if (is_running_in_flash()) {
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/*
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* if running from flash, jump to small relocated code
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* area in SRAM.
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*/
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p0 = readl(&prcm_base->clken_pll);
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sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
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sr32(&p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
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p1 = readl(&prcm_base->clksel1_pll);
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sr32(&p1, 27, 2, dpll_param_p->m2); /* Set M2 */
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sr32(&p1, 16, 11, dpll_param_p->m); /* Set M */
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sr32(&p1, 8, 7, dpll_param_p->n); /* Set N */
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sr32(&p1, 6, 1, 0); /* set source for 96M */
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p2 = readl(&prcm_base->clksel_core);
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sr32(&p2, 8, 4, CORE_SSI_DIV); /* ssi */
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sr32(&p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
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sr32(&p2, 2, 2, CORE_L4_DIV); /* l4 */
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sr32(&p2, 0, 2, CORE_L3_DIV); /* l3 */
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p3 = (u32)&prcm_base->idlest_ckgen;
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(*f_lock_pll) (p0, p1, p2, p3);
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}
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/* PER DPLL */
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sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
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wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
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/* Getting the base address to PER DPLL param table */
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/* Set N */
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dpll_param_p = (dpll_param *) get_per_dpll_param();
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/* Moving it to the right sysclk base */
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dpll_param_p = dpll_param_p + clk_index;
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/*
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* Errata 1.50 Workaround for OMAP3 ES1.0 only
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* If using default divisors, write default divisor + 1
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* and then the actual divisor value
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*/
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sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2 + 1); /* set M6 */
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sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2); /* set M6 */
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sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2 + 1); /* set M5 */
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sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2); /* set M5 */
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sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2 + 1); /* set M4 */
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sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2); /* set M4 */
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sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2 + 1); /* set M3 */
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sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2); /* set M3 */
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sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
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sr32(&prcm_base->clksel3_pll, 0, 5, dpll_param_p->m2); /* set M2 */
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/* Workaround end */
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sr32(&prcm_base->clksel2_pll, 8, 11, dpll_param_p->m); /* set m */
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sr32(&prcm_base->clksel2_pll, 0, 7, dpll_param_p->n); /* set n */
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sr32(&prcm_base->clken_pll, 20, 4, dpll_param_p->fsel); /* FREQSEL */
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sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK); /* lock mode */
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wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
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/* Getting the base address to MPU DPLL param table */
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dpll_param_p = (dpll_param *) get_mpu_dpll_param();
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/* Moving it to the right sysclk and ES rev base */
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dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
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/* MPU DPLL (unlocked already) */
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/* Set M2 */
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sr32(&prcm_base->clksel2_pll_mpu, 0, 5, dpll_param_p->m2);
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/* Set M */
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sr32(&prcm_base->clksel1_pll_mpu, 8, 11, dpll_param_p->m);
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/* Set N */
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sr32(&prcm_base->clksel1_pll_mpu, 0, 7, dpll_param_p->n);
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/* FREQSEL */
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sr32(&prcm_base->clken_pll_mpu, 4, 4, dpll_param_p->fsel);
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/* lock mode */
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sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
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wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY);
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/* Getting the base address to IVA DPLL param table */
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dpll_param_p = (dpll_param *) get_iva_dpll_param();
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/* Moving it to the right sysclk and ES rev base */
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dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
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/* IVA DPLL (set to 12*20=240MHz) */
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sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
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wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
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/* set M2 */
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sr32(&prcm_base->clksel2_pll_iva2, 0, 5, dpll_param_p->m2);
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/* set M */
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sr32(&prcm_base->clksel1_pll_iva2, 8, 11, dpll_param_p->m);
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/* set N */
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sr32(&prcm_base->clksel1_pll_iva2, 0, 7, dpll_param_p->n);
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/* FREQSEL */
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sr32(&prcm_base->clken_pll_iva2, 4, 4, dpll_param_p->fsel);
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/* lock mode */
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sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
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wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
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/* Set up GPTimers to sys_clk source only */
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sr32(&prcm_base->clksel_per, 0, 8, 0xff);
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sr32(&prcm_base->clksel_wkup, 0, 1, 1);
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sdelay(5000);
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}
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/******************************************************************************
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* peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
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*****************************************************************************/
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void per_clocks_enable(void)
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{
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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/* Enable GP2 timer. */
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sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
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sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
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sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
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#ifdef CONFIG_SYS_NS16550
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/* Enable UART1 clocks */
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sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
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sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
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/* UART 3 Clocks */
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sr32(&prcm_base->fclken_per, 11, 1, 0x1);
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sr32(&prcm_base->iclken_per, 11, 1, 0x1);
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#endif
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#ifdef CONFIG_DRIVER_OMAP34XX_I2C
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/* Turn on all 3 I2C clocks */
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sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
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sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
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#endif
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/* Enable the ICLK for 32K Sync Timer as its used in udelay */
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sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
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sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
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sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
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sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
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sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
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sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
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sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
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sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
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sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
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sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
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sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
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sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
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sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
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sdelay(1000);
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}
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