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https://github.com/AsahiLinux/u-boot
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1fd54253bc
The a3700_fdt_fix_pcie_regions() function still computes nonsense.
It computes the fixup offset from the PCI address taken from the first
row of the "ranges" array, which means that:
- PCI address must equal CPU address (otherwise the computed fix offset
will be wrong),
- the first row must contain the lowest address.
This is the case for the default device-tree, which is why we didn't
notice it.
It also adds the fixup offset to all PCI and CPU addresses, which is
wrong.
Instead:
1) The fixup offset must be computed from the CPU address, not PCI
address.
2) The fixup offset must be computed from the row containing the lowest
CPU address, which is not necessarily contained in the first row.
3) The PCI address - the address to which the PCIe controller remaps the
address space as seen from the point of view of the PCIe device -
must be fixed by the fix offset in the same way as the CPU address
only in the special case when the CPU adn PCI addresses are the same.
Same addresses means that remapping is disabled, and thus if we
change the CPU address, we need also to change the PCI address so
that the remapping is still disabled afterwards.
Consider an example:
The ranges entries contain:
PCI address CPU address
70000000 EA000000
E9000000 E9000000
EB000000 EB000000
By default CPU PCIe window is at: E8000000 - F0000000
Consider the case when TF-A moves it to: F2000000 - FA000000
Until now the function would take the PCI address of the first entry:
70000000, and the new base, F2000000, to compute the fix offset:
F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses,
resulting in
PCI address CPU address
F2000000 6C000000
6B000000 6B000000
6D000000 6D000000
which is complete nonsense - none of the CPU addresses is in the
requested window.
Now it will take the lowest CPU address, which is in second row,
E9000000, and compute the fix offset F2000000 - E9000000 = 09000000,
and then add it to all CPU addresses and those PCI addresses which
equal to their corresponding CPU addresses, resulting in
PCI address CPU address
70000000 F3000000
F2000000 F2000000
F4000000 F4000000
where all of the CPU addresses are in the needed window.
Fixes: 4a82fca8e3
("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function")
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
440 lines
11 KiB
C
440 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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* Copyright (C) 2020 Marek Behun <marek.behun@nic.cz>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <linux/bitops.h>
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#include <linux/libfdt.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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#include <sort.h>
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/* Armada 3700 */
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#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
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#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
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#define MVEBU_XTAL_MODE_MASK BIT(9)
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#define MVEBU_XTAL_MODE_OFFS 9
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#define MVEBU_XTAL_CLOCK_25MHZ 0x0
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#define MVEBU_XTAL_CLOCK_40MHZ 0x1
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#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
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#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
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/* Armada 3700 CPU Address Decoder registers */
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#define MVEBU_CPU_DEC_WIN_REG_BASE (size_t)(MVEBU_REGISTER(0xcf00))
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#define MVEBU_CPU_DEC_WIN_CTRL(w) \
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(MVEBU_CPU_DEC_WIN_REG_BASE + ((w) << 4))
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#define MVEBU_CPU_DEC_WIN_CTRL_EN BIT(0)
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK 0xf
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS 4
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM 0
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#define MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE 2
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#define MVEBU_CPU_DEC_WIN_SIZE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x4)
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#define MVEBU_CPU_DEC_WIN_BASE(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0x8)
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#define MVEBU_CPU_DEC_WIN_REMAP(w) (MVEBU_CPU_DEC_WIN_CTRL(w) + 0xc)
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#define MVEBU_CPU_DEC_WIN_GRANULARITY 16
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#define MVEBU_CPU_DEC_WINS 5
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#define MVEBU_CPU_DEC_CCI_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xe0)
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#define MVEBU_CPU_DEC_ROM_BASE (MVEBU_CPU_DEC_WIN_REG_BASE + 0xf4)
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#define MAX_MEM_MAP_REGIONS (MVEBU_CPU_DEC_WINS + 4)
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#define A3700_PTE_BLOCK_NORMAL \
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(PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE)
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#define A3700_PTE_BLOCK_DEVICE \
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(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
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DECLARE_GLOBAL_DATA_PTR;
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static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
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{
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/*
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* SRAM, MMIO regions
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* Don't remove this, build_mem_map needs it.
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*/
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.phys = SOC_REGS_PHY_BASE,
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.virt = SOC_REGS_PHY_BASE,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = A3700_PTE_BLOCK_DEVICE
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},
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};
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struct mm_region *mem_map = mvebu_mem_map;
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static int get_cpu_dec_win(int win, u32 *tgt, u32 *base, u32 *size)
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{
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u32 reg;
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reg = readl(MVEBU_CPU_DEC_WIN_CTRL(win));
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if (!(reg & MVEBU_CPU_DEC_WIN_CTRL_EN))
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return -1;
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if (tgt) {
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reg >>= MVEBU_CPU_DEC_WIN_CTRL_TGT_OFFS;
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reg &= MVEBU_CPU_DEC_WIN_CTRL_TGT_MASK;
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*tgt = reg;
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}
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if (base) {
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reg = readl(MVEBU_CPU_DEC_WIN_BASE(win));
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*base = reg << MVEBU_CPU_DEC_WIN_GRANULARITY;
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}
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if (size) {
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/*
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* Window size is encoded as the number of 1s from LSB to MSB,
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* followed by 0s. The number of 1s specifies the size in 64 KiB
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* granularity.
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*/
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reg = readl(MVEBU_CPU_DEC_WIN_SIZE(win));
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*size = ((reg + 1) << MVEBU_CPU_DEC_WIN_GRANULARITY);
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}
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return 0;
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}
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/*
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* Builds mem_map according to CPU Address Decoder settings, which were set by
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* the TIMH image on the Cortex-M3 secure processor, or by ARM Trusted Firmware
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*/
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static void build_mem_map(void)
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{
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int win, region;
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u32 reg;
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region = 1;
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/* CCI-400 */
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reg = readl(MVEBU_CPU_DEC_CCI_BASE);
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mvebu_mem_map[region].phys = reg << 20;
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mvebu_mem_map[region].virt = reg << 20;
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mvebu_mem_map[region].size = SZ_64K;
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mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_DEVICE;
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++region;
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/* AP BootROM */
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reg = readl(MVEBU_CPU_DEC_ROM_BASE);
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mvebu_mem_map[region].phys = reg << 20;
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mvebu_mem_map[region].virt = reg << 20;
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mvebu_mem_map[region].size = SZ_1M;
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mvebu_mem_map[region].attrs = A3700_PTE_BLOCK_NORMAL;
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++region;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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u64 attrs;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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attrs = A3700_PTE_BLOCK_NORMAL;
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else if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
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attrs = A3700_PTE_BLOCK_DEVICE;
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else
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/* skip windows with other targets */
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continue;
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mvebu_mem_map[region].phys = base;
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mvebu_mem_map[region].virt = base;
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mvebu_mem_map[region].size = size;
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mvebu_mem_map[region].attrs = attrs;
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++region;
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}
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/* add list terminator */
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mvebu_mem_map[region].size = 0;
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mvebu_mem_map[region].attrs = 0;
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}
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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int a3700_dram_init(void)
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{
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int win;
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build_mem_map();
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gd->ram_size = 0;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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/* skip non-DRAM windows */
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if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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continue;
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/*
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* It is possible that one image was built for boards with
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* different RAM sizes, for example 512 MiB and 1 GiB.
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* We therefore try to determine the actual RAM size in the
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* window with get_ram_size.
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*/
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gd->ram_size += get_ram_size((void *)(size_t)base, size);
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}
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return 0;
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}
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struct a3700_dram_window {
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size_t base, size;
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};
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static int dram_win_cmp(const void *a, const void *b)
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{
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size_t ab, bb;
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ab = ((const struct a3700_dram_window *)a)->base;
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bb = ((const struct a3700_dram_window *)b)->base;
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if (ab < bb)
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return -1;
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else if (ab > bb)
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return 1;
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else
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return 0;
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}
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int a3700_dram_init_banksize(void)
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{
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struct a3700_dram_window dram_wins[MVEBU_CPU_DEC_WINS];
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int bank, win, ndram_wins;
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u32 last_end;
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size_t size;
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ndram_wins = 0;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt, size;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, &size))
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continue;
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/* skip non-DRAM windows */
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if (tgt != MVEBU_CPU_DEC_WIN_CTRL_TGT_DRAM)
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continue;
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dram_wins[win].base = base;
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dram_wins[win].size = size;
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++ndram_wins;
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}
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qsort(dram_wins, ndram_wins, sizeof(dram_wins[0]), dram_win_cmp);
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bank = 0;
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last_end = -1;
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for (win = 0; win < ndram_wins; ++win) {
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/* again determining actual RAM size as in a3700_dram_init */
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size = get_ram_size((void *)dram_wins[win].base,
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dram_wins[win].size);
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/*
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* Check if previous window ends as the current starts. If yes,
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* merge these windows into one "bank". This is possible by this
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* simple check thanks to mem_map regions being qsorted in
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* build_mem_map.
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*/
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if (last_end == dram_wins[win].base) {
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gd->bd->bi_dram[bank - 1].size += size;
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last_end += size;
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} else {
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if (bank == CONFIG_NR_DRAM_BANKS) {
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printf("Need more CONFIG_NR_DRAM_BANKS\n");
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return -ENOBUFS;
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}
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gd->bd->bi_dram[bank].start = dram_wins[win].base;
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gd->bd->bi_dram[bank].size = size;
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last_end = dram_wins[win].base + size;
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++bank;
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}
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}
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/*
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* If there is more place for DRAM BANKS definitions than needed, fill
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* the rest with zeros.
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*/
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for (; bank < CONFIG_NR_DRAM_BANKS; ++bank) {
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gd->bd->bi_dram[bank].start = 0;
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gd->bd->bi_dram[bank].size = 0;
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}
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return 0;
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}
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static u32 find_pcie_window_base(void)
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{
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int win;
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for (win = 0; win < MVEBU_CPU_DEC_WINS; ++win) {
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u32 base, tgt;
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/* skip disabled windows */
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if (get_cpu_dec_win(win, &tgt, &base, NULL))
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continue;
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if (tgt == MVEBU_CPU_DEC_WIN_CTRL_TGT_PCIE)
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return base;
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}
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return -1;
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}
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static int fdt_setprop_inplace_u32_partial(void *blob, int node,
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const char *name,
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u32 idx, u32 val)
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{
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val = cpu_to_fdt32(val);
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return fdt_setprop_inplace_namelen_partial(blob, node, name,
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strlen(name),
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idx * sizeof(u32),
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&val, sizeof(u32));
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}
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int a3700_fdt_fix_pcie_regions(void *blob)
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{
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u32 base, lowest_cpu_addr, fix_offset;
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int pci_cells, cpu_cells, size_cells;
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const u32 *ranges;
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int node, pnode;
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int ret, i, len;
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base = find_pcie_window_base();
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if (base == -1)
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return -ENOENT;
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node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
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if (node < 0)
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return node;
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ranges = fdt_getprop(blob, node, "ranges", &len);
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if (!ranges || !len || len % sizeof(u32))
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return -EINVAL;
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/*
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* The "ranges" property is an array of
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* { <PCI address> <CPU address> <size in PCI address space> }
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* where number of PCI address cells and size cells is stored in the
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* "#address-cells" and "#size-cells" properties of the same node
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* containing the "ranges" property and number of CPU address cells
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* is stored in the parent's "#address-cells" property.
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*
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* All 3 elements can span a diffent number of cells. Fetch them.
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*/
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pnode = fdt_parent_offset(blob, node);
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pci_cells = fdt_address_cells(blob, node);
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cpu_cells = fdt_address_cells(blob, pnode);
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size_cells = fdt_size_cells(blob, node);
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/* PCI addresses always use 3 cells */
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if (pci_cells != 3)
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return -EINVAL;
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/* CPU addresses on Armada 37xx always use 2 cells */
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if (cpu_cells != 2)
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return -EINVAL;
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for (i = 0; i < len / sizeof(u32);
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i += pci_cells + cpu_cells + size_cells) {
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/*
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* Parent CPU addresses on Armada 37xx are always 32-bit, so
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* check that the high word is zero.
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*/
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if (fdt32_to_cpu(ranges[i + pci_cells]))
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return -EINVAL;
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if (i == 0 ||
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fdt32_to_cpu(ranges[i + pci_cells + 1]) < lowest_cpu_addr)
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lowest_cpu_addr = fdt32_to_cpu(ranges[i + pci_cells + 1]);
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}
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/* Calculate fixup offset from the lowest (first) CPU address */
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fix_offset = base - lowest_cpu_addr;
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/* If fixup offset is zero there is nothing to fix */
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if (!fix_offset)
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return 0;
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/*
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* Fix each CPU address and corresponding PCI address if PCI address
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* is not already remapped (has the same value)
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*/
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for (i = 0; i < len / sizeof(u32);
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i += pci_cells + cpu_cells + size_cells) {
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u32 cpu_addr;
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u64 pci_addr;
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int idx;
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/* Fix CPU address */
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idx = i + pci_cells + cpu_cells - 1;
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cpu_addr = fdt32_to_cpu(ranges[idx]);
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ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
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cpu_addr + fix_offset);
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if (ret)
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return ret;
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/* Fix PCI address only if it isn't remapped (is same as CPU) */
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idx = i + pci_cells - 1;
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pci_addr = ((u64)fdt32_to_cpu(ranges[idx - 1]) << 32) |
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fdt32_to_cpu(ranges[idx]);
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if (cpu_addr != pci_addr)
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continue;
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ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
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cpu_addr + fix_offset);
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if (ret)
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return ret;
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}
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return 0;
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}
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void reset_cpu(void)
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{
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/*
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* Write magic number of 0x1d1e to North Bridge Warm Reset register
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* to trigger warm reset
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*/
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writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz (25 or 40)
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*/
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u32 get_ref_clk(void)
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{
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u32 regval;
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regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
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MVEBU_XTAL_MODE_OFFS;
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if (regval == MVEBU_XTAL_CLOCK_25MHZ)
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return 25;
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else
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return 40;
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}
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