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9352697aa0
This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.
As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
SW5.1 (NAND_BOOTn) = OFF (logic-1)
SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */
SW5.3 (eMMC_BOOTn) = OFF (logic-1)
SW5.4 (QSPI_BOOTn) = OFF (logic-1)
And also set appropriate SYSBOOT configurations:
SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */
SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */
SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */
SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */
Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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*
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* Author
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* Initial Code from:
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MEM_H_
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#define _MEM_H_
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/*
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* GPMC settings -
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* Definitions is as per the following format
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* #define <PART>_GPMC_CONFIG<x> <value>
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* Where:
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* PART is the part name e.g. STNOR - Intel Strata Flash
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* x is GPMC config registers from 1 to 6 (there will be 6 macros)
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* Value is corresponding value
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*
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* For every valid PRCM configuration there should be only one definition of
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* the same. if values are independent of the board, this definition will be
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* present in this file if values are dependent on the board, then this should
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* go into corresponding mem-boardName.h file
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*
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* Currently valid part Names are (PART):
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* M_NAND - Micron NAND
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* STNOR - STMicrolelctronics M29W128GL
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*/
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#define GPMC_SIZE_256M 0x0
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#define GPMC_SIZE_128M 0x8
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#define GPMC_SIZE_64M 0xC
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#define GPMC_SIZE_32M 0xE
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#define GPMC_SIZE_16M 0xF
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#define M_NAND_GPMC_CONFIG1 0x00000800
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#define M_NAND_GPMC_CONFIG2 0x001e1e00
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#define M_NAND_GPMC_CONFIG3 0x001e1e00
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#define M_NAND_GPMC_CONFIG4 0x16051807
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#define M_NAND_GPMC_CONFIG5 0x00151e1e
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#define M_NAND_GPMC_CONFIG6 0x16000f80
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#define M_NAND_GPMC_CONFIG7 0x00000008
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#define STNOR_GPMC_CONFIG1 0x00001000
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#define STNOR_GPMC_CONFIG2 0x001f1f00
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#define STNOR_GPMC_CONFIG3 0x001f1f01
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#define STNOR_GPMC_CONFIG4 0x1f011f01
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#define STNOR_GPMC_CONFIG5 0x001d1f1f
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#define STNOR_GPMC_CONFIG6 0x08070280
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#define STNOR_GPMC_CONFIG7 0x00000048
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/* max number of GPMC Chip Selects */
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#define GPMC_MAX_CS 8
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/* max number of GPMC regs */
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#define GPMC_MAX_REG 7
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#endif /* endif _MEM_H_ */
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