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Ashish Kumar 63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus 
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
..
Kconfig NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUST 2017-01-24 10:33:59 -05:00
ls1012aqds.c fsl-layerscape: Consolidate registers space defination for CCI-400 bus 2017-09-11 07:55:36 -07:00
ls1012aqds_qixis.h
MAINTAINERS
Makefile
README

README 

Overview
--------
QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.

LS1012A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
SoC overview.

LS1012AQDS board Overview
-----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express - 3.0
      - SGMII, SGMII 2.5
      - SATA 3.0
 - DDR Controller
     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
 - QSPI Controller
     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
       emulator
 - USB 3.0
    - One USB 3.0 controller with integrated PHY
    - One high-speed USB 3.0 port
 - USB 2.0
    - One USB 2.0 controller with ULPI interface
 - Two enhanced secure digital host controllers:
    - SDHC1 controller can be connected to onboard SDHC connector
    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
 - 2 I2C controllers
 - One SATA onboard connectors
 - UART
 - 5 SAI
    - One SAI port with audio codec SGTL5000:
	• Provides MIC bias
	• Provides headphone and line output
    - One SAI port terminated at 2x6 header
    - Three SAI Tx/Rx ports terminated at 2x3 headers
 - ARM JTAG support

Booting Options
---------------
a) QSPI Flash Emu Boot
b) QSPI Flash 1
c) QSPI Flash 2

QSPI flash map
--------------
Images		| Size	|QSPI Flash Address
------------------------------------------
RCW + PBI	| 1MB	| 0x4000_0000
U-boot 		| 1MB	| 0x4010_0000
U-boot Env 	| 1MB	| 0x4020_0000
PPA FIT image	| 2MB	| 0x4050_0000
Linux ITB	| ~53MB | 0x40A0_0000