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3d80ec5265
Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC and follows 96boards specification, so it's compatible with 96boards mezzanine boards [2]. This patch enables next features: * Serial console * USI * PMU (muxing AP UART path) * Pinctrl * Clocks * Timer (ARMv8 architected) * Reset control It's quite a minimal enablement. Features like MMC, USB and Ethernet will be enabled later. The rationale for config values is as follows: * TEXT_BASE = 0xf8800000 That's where BL2 loads the U-Boot payload, so TEXT_BASE must be exactly this value. Overall the memory map is designed in a way to keep the bootloader in the upper 128 MiB area of RAM, which is 0xf8000000..0xffffffff. That includes bootloader's code, stack, data, heap, MMU tables, etc. All the memory below that 128 MiB chunk can be used for storing boot images (0x80000000..0xf8000000). * CUSTOM_SYS_INIT_SP_ADDR = 0xf8c00000 Just 4 MiB above the TEXT_BASE address, to leave enough space for U-Boot code and stack itself (grows downwards). * SYS_LOAD_ADDR = 0x80000000 The beginning of RAM. That's where Linux kernel image must be loaded. * SYS_MALLOC_LEN = 0x81f000 8 MiB for malloc() + ENV_SIZE (128 KiB) * SYS_MALLOC_F_LEN = 0x4000 Increase malloc() pool size available before relocation from 8 KiB (default) to 16 KiB. Otherwise "alloc space exhausted" message appears in U-Boot log during board_init_f() stage. There are next reasons for doing so: 1. Having "bootph-all" flags in some dts nodes leads to binding those during pre-relocation stage, and binding (DM) uses dynamic memory allocation 2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic memory allocation Device tree file was imported from Linux kernel. All nodes and boot phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to enable serial console: * oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks * pinctrl_alive and uart1_pins: needed to mux UART pins * pmu_system_controller: configures AP UART path to uart1_pins * usi_uart: configures USI block to operate as a UART protocol * serial_0: enables serial console (UART) [1] https://www.96boards.org/product/e850-96b/ [2] https://www.96boards.org/products/mezzanine/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
21 lines
567 B
Text
21 lines
567 B
Text
CONFIG_ARM=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_TEXT_BASE=0xf8800000
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CONFIG_SYS_MALLOC_LEN=0x81f000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_ARCH_EXYNOS9=y
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000
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CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96"
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CONFIG_SYS_LOAD_ADDR=0x80000000
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# CONFIG_AUTOBOOT is not set
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_NET is not set
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CONFIG_CLK_EXYNOS850=y
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# CONFIG_MMC is not set
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CONFIG_SOC_SAMSUNG=y
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CONFIG_EXYNOS_PMU=y
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CONFIG_EXYNOS_USI=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_SYSCON=y
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