mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
5b8031ccb4
In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/*
|
|
* Copyright 2008 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <fsl_ddr_sdram.h>
|
|
|
|
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
|
|
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
|
|
#endif
|
|
|
|
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
|
|
unsigned int ctrl_num, int step)
|
|
{
|
|
unsigned int i;
|
|
struct ccsr_ddr __iomem *ddr =
|
|
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
|
|
|
|
if (ctrl_num != 0) {
|
|
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
if (i == 0) {
|
|
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
|
|
out_be32(&ddr->cs0_config, regs->cs[i].config);
|
|
|
|
} else if (i == 1) {
|
|
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
|
|
out_be32(&ddr->cs1_config, regs->cs[i].config);
|
|
|
|
} else if (i == 2) {
|
|
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
|
|
out_be32(&ddr->cs2_config, regs->cs[i].config);
|
|
|
|
} else if (i == 3) {
|
|
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
|
|
out_be32(&ddr->cs3_config, regs->cs[i].config);
|
|
}
|
|
}
|
|
|
|
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
|
|
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
|
|
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
|
|
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
|
|
#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
|
|
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
|
|
#endif
|
|
|
|
/*
|
|
* 200 painful micro-seconds must elapse between
|
|
* the DDR clock setup and the DDR config enable.
|
|
*/
|
|
udelay(200);
|
|
asm volatile("sync;isync");
|
|
|
|
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
|
|
|
|
asm("sync;isync;msync");
|
|
udelay(500);
|
|
}
|
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
|
/*
|
|
* Initialize all of memory for ECC, then enable errors.
|
|
*/
|
|
|
|
void
|
|
ddr_enable_ecc(unsigned int dram_size)
|
|
{
|
|
struct ccsr_ddr __iomem *ddr =
|
|
(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
|
|
|
|
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
|
|
|
|
/*
|
|
* Enable errors for ECC.
|
|
*/
|
|
debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
|
|
ddr->err_disable = 0x00000000;
|
|
asm("sync;isync;msync");
|
|
debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
|
|
}
|
|
|
|
#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */
|