mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 08:59:33 +00:00
ee75f16868
TPL max size is limited to 184 KB, SPL is loaded to 0x0 and TF-A is loaded to 0x40000, this limit SPL max size to 256 KB. With BootRom only reading first 2 KB per 4 KB page of SPI flash, 880 KB may be needed for TPL+SPL in a worst-case scenario. (184 KB + 256 KB) x 2 = 880 KB Use 0xE0000 (896 KB) as the payload offset in SPI flash, this allows for a payload of 3168 KB before env offset start to overlap. Also add CONFIG_ROCKCHIP_SPI_IMAGE=y to build a bootable SPI flash image, u-boot-rockchip-spi.bin. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <foss+u-boot@0leil.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
102 lines
2.7 KiB
Text
102 lines
2.7 KiB
Text
CONFIG_ARM=y
|
|
CONFIG_SKIP_LOWLEVEL_INIT=y
|
|
CONFIG_COUNTER_FREQUENCY=24000000
|
|
CONFIG_ARCH_ROCKCHIP=y
|
|
CONFIG_TEXT_BASE=0x00200000
|
|
CONFIG_SPL_GPIO=y
|
|
CONFIG_NR_DRAM_BANKS=1
|
|
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
|
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
|
|
CONFIG_ENV_SIZE=0x8000
|
|
CONFIG_ENV_OFFSET=0x3F8000
|
|
CONFIG_ENV_SECT_SIZE=0x1000
|
|
CONFIG_DEFAULT_DEVICE_TREE="rk3399-roc-pc-mezzanine"
|
|
CONFIG_DM_RESET=y
|
|
CONFIG_ROCKCHIP_RK3399=y
|
|
CONFIG_ROCKCHIP_SPI_IMAGE=y
|
|
CONFIG_TARGET_ROC_PC_RK3399=y
|
|
CONFIG_SPL_STACK=0x400000
|
|
CONFIG_DEBUG_UART_BASE=0xFF1A0000
|
|
CONFIG_DEBUG_UART_CLOCK=24000000
|
|
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
|
CONFIG_SPL_SPI=y
|
|
CONFIG_SYS_LOAD_ADDR=0x800800
|
|
CONFIG_PCI=y
|
|
CONFIG_DEBUG_UART=y
|
|
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
|
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
|
|
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
|
CONFIG_MISC_INIT_R=y
|
|
CONFIG_SPL_MAX_SIZE=0x40000
|
|
CONFIG_SPL_PAD_TO=0x7f8000
|
|
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
|
CONFIG_SPL_BSS_START_ADDR=0x400000
|
|
CONFIG_SPL_BSS_MAX_SIZE=0x2000
|
|
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
|
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
|
CONFIG_SPL_STACK_R=y
|
|
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20000
|
|
CONFIG_SPL_ENV_SUPPORT=y
|
|
CONFIG_SPL_SPI_LOAD=y
|
|
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
|
|
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
|
CONFIG_TPL=y
|
|
CONFIG_CMD_BOOTZ=y
|
|
CONFIG_CMD_GPT=y
|
|
CONFIG_CMD_MMC=y
|
|
CONFIG_CMD_PCI=y
|
|
CONFIG_CMD_USB=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
CONFIG_CMD_TIME=y
|
|
CONFIG_SPL_OF_CONTROL=y
|
|
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
|
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
CONFIG_SPL_DM_SEQ_ALIAS=y
|
|
CONFIG_ROCKCHIP_GPIO=y
|
|
CONFIG_SYS_I2C_ROCKCHIP=y
|
|
CONFIG_MISC=y
|
|
CONFIG_ROCKCHIP_EFUSE=y
|
|
CONFIG_MMC_DW=y
|
|
CONFIG_MMC_DW_ROCKCHIP=y
|
|
CONFIG_MMC_SDHCI=y
|
|
CONFIG_MMC_SDHCI_ROCKCHIP=y
|
|
CONFIG_SF_DEFAULT_BUS=1
|
|
CONFIG_SPI_FLASH_WINBOND=y
|
|
CONFIG_ETH_DESIGNWARE=y
|
|
CONFIG_GMAC_ROCKCHIP=y
|
|
CONFIG_NVME_PCI=y
|
|
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
|
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
|
CONFIG_PMIC_RK8XX=y
|
|
CONFIG_REGULATOR_PWM=y
|
|
CONFIG_REGULATOR_RK8XX=y
|
|
CONFIG_PWM_ROCKCHIP=y
|
|
# CONFIG_RAM_ROCKCHIP_DEBUG is not set
|
|
CONFIG_RAM_ROCKCHIP_LPDDR4=y
|
|
CONFIG_BAUDRATE=1500000
|
|
CONFIG_DEBUG_UART_SHIFT=2
|
|
CONFIG_SYS_NS16550_MEM32=y
|
|
CONFIG_ROCKCHIP_SPI=y
|
|
CONFIG_SYSRESET=y
|
|
CONFIG_USB=y
|
|
CONFIG_USB_XHCI_HCD=y
|
|
CONFIG_USB_XHCI_DWC3=y
|
|
CONFIG_USB_EHCI_HCD=y
|
|
CONFIG_USB_EHCI_GENERIC=y
|
|
CONFIG_USB_DWC3=y
|
|
CONFIG_USB_DWC3_GENERIC=y
|
|
CONFIG_USB_KEYBOARD=y
|
|
CONFIG_USB_HOST_ETHER=y
|
|
CONFIG_USB_ETHER_ASIX=y
|
|
CONFIG_USB_ETHER_ASIX88179=y
|
|
CONFIG_USB_ETHER_MCS7830=y
|
|
CONFIG_USB_ETHER_RTL8152=y
|
|
CONFIG_USB_ETHER_SMSC95XX=y
|
|
CONFIG_USB_GADGET=y
|
|
CONFIG_VIDEO=y
|
|
CONFIG_DISPLAY=y
|
|
CONFIG_VIDEO_ROCKCHIP=y
|
|
CONFIG_DISPLAY_ROCKCHIP_HDMI=y
|
|
CONFIG_SPL_TINY_MEMSET=y
|
|
CONFIG_ERRNO_STR=y
|