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df8a24cdd3
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
47 lines
1.4 KiB
Makefile
47 lines
1.4 KiB
Makefile
#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# AMCC 405EZ Reference Platform (Acadia) board
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#
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#
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# TEXT_BASE for SPL:
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#
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# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
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# in the last 4kBytes of memory space in cache.
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# We will copy this SPL into internal SRAM in start.S. So we set
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# TEXT_BASE to starting address in internal SRAM here.
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#
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TEXT_BASE = 0xf8004000
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# PAD_TO used to generate a 16kByte binary needed for the combined image
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# -> PAD_TO = TEXT_BASE + 0x4000
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PAD_TO = 0xf8008000
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
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endif
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