mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 13:14:27 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
98 lines
2.2 KiB
C
98 lines
2.2 KiB
C
/*
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* Vitesse 7385 Switch Firmware Upload
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
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* under the terms of the GNU General Public License version 2. This
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* program is licensed "as is" without any warranty of any kind, whether
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* express or implied.
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*
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* This module uploads proprietary firmware for the Vitesse VSC7385 5-port
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* switch.
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*/
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#include <config.h>
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#include <common.h>
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#include <console.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include "vsc7385.h"
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/*
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* Upload a Vitesse VSC7385 firmware image to the hardware
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*
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* This function takes a pointer to a VSC7385 firmware image and a size, and
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* uploads that firmware to the VSC7385.
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*
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* This firmware is typically located at a board-specific flash address,
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* and the size is typically 8KB.
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*
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* The firmware is Vitesse proprietary.
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*
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* Further details on the register information can be obtained from Vitesse.
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*/
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int vsc7385_upload_firmware(void *firmware, unsigned int size)
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{
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u8 *fw = firmware;
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unsigned int i;
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u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
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u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
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u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
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u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
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u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
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#ifdef DEBUG
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u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
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#endif
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out_be32(gloreset, 3);
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udelay(200);
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out_be32(icpu_ctrl, 0x8E);
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udelay(20);
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out_be32(icpu_rom_map, 1);
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udelay(20);
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/* Write the firmware to I-RAM */
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out_be32(icpu_addr, 0);
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udelay(20);
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for (i = 0; i < size; i++) {
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out_be32(icpu_data, fw[i]);
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udelay(20);
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if (ctrlc())
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return -EINTR;
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}
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/* Read back and compare */
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out_be32(icpu_addr, 0);
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udelay(20);
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for (i = 0; i < size; i++) {
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u8 value;
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value = (u8) in_be32(icpu_data);
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udelay(20);
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if (value != fw[i]) {
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debug("VSC7385: Upload mismatch: address 0x%x, "
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"read value 0x%x, image value 0x%x\n",
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i, value, fw[i]);
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return -EIO;
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}
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if (ctrlc())
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break;
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}
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out_be32(icpu_ctrl, 0x0B);
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udelay(20);
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#ifdef DEBUG
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printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
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udelay(20);
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#endif
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return 0;
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}
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