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The PLL1 node (st,pll1) is optional in device tree, the max supported frequency define in OPP node is used when the node is absent. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
405 lines
9.4 KiB
Text
405 lines
9.4 KiB
Text
STMicroelectronics STM32MP1 clock tree initialization
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=====================================================
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The STM32MP1 clock tree initialization is based on device tree information
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for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
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RCC IP = st,stm32mp1-rcc
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========================
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The RCC IP is both a reset and a clock controller but this documentation only
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describes the fields added for clock tree initialization which are not present
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in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
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file.
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This parent node may optionally have additional children nodes which define
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specific init values for RCC elements.
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The added properties for clock tree initialization are:
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Required properties:
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- st,clksrc : The clock sources configuration array in a platform specific
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order.
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For the STM32MP15x family there are 9 clock sources selector which are
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configured in the following order:
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MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
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Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
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from dt-bindings/clock/stm32mp1-clksrc.h.
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Example:
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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- st,clkdiv : The clock main dividers value specified in an array
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in a platform specific order.
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When used, it shall describe the whole clock dividers tree.
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For the STM32MP15x family there are 11 dividers values expected.
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They shall be configured in the following order:
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MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
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The each divider value uses the DIV coding defined in RCC associated
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register RCC_xxxDIVR. In most the case, it is:
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0x0: not divided
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0x1: division by 2
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0x2: division by 4
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0x3: division by 8
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...
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Note that for RTC MCO1 MCO2, the coding is different:
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0x0: not divided
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0x1: division by 2
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0x2: division by 3
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0x3: division by 4
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...
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Example:
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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Optional Properties:
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- children for a PLL configuration with "st,stm32mp1-pll" compatible
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each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
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are listed with associated reg 0 to 3.
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PLLx is off when the associated node is absent or deactivated.
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For PLL1, when the node is absent, the frequency of the OPP node is used
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to compute the PLL setting (see compatible "operating-points-v2" in
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opp/opp.txt for details).
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Here are the available properties for each PLL node:
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- compatible: should be "st,stm32mp1-pll"
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- reg: index of the pll instance
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- cfg: The parameters for PLL configuration in the following order:
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DIVM DIVN DIVP DIVQ DIVR Output.
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DIVx values are defined as in RCC spec:
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0x0: bypass (division by 1)
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0x1: division by 2
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0x2: division by 3
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0x3: division by 4
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...
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Output contains a bitfield for each output value (1:ON/0:OFF)
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BIT(0) => output P : DIVPEN
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BIT(1) => output Q : DIVQEN
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BIT(2) => output R : DIVREN
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NB: macro PQR(p,q,r) can be used to build this value
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with p,q,r = 0 or 1.
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- frac : Fractional part of the multiplication factor
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(optional, PLL is in integer mode when absent).
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- csg : Clock Spreading Generator (optional) with parameters in the
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following order: MOD_PER INC_STEP SSCG_MODE.
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MOD_PER: Modulation Period Adjustment
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INC_STEP: Modulation Depth Adjustment
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SSCG_MODE: Spread spectrum clock generator mode, with associated
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defined from stm32mp1-clksrc.h:
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- SSCG_MODE_CENTER_SPREAD = 0
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- SSCG_MODE_DOWN_SPREAD = 1
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Example:
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st,pll@0 {
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compatible = "st,stm32mp1-pll";
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reg = <0>;
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cfg = < 1 53 0 0 0 1 >;
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frac = < 0x810 >;
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};
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st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 1 43 1 0 0 PQR(0,1,1) >;
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csg = < 10 20 1 >;
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};
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st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 2 85 3 13 3 0 >;
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csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
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};
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st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 2 78 4 7 9 3 >;
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};
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- st,pkcs : used to configure the peripherals kernel clock selection.
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The property is a list of peripheral kernel clock source identifiers defined
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by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
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dt-bindings/clock/stm32mp1-clksrc.h.
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st,pkcs may not list all the kernel clocks and has no ordering requirements.
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Example:
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st,pkcs = <
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CLK_STGEN_HSE
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CLK_CKPER_HSI
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CLK_USBPHY_PLL2P
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CLK_DSI_PLL2Q
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CLK_I2C46_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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>;
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other clocks = fixed-clock
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==========================
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The clock tree is also based on 5 fixed-clock in clocks node
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used to define the state of associated ST32MP1 oscillators:
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- clk-lsi
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- clk-lse
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- clk-hsi
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- clk-hse
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- clk-csi
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At boot the clock tree initialization will
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- enable oscillators present in device tree and not disabled
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(node with status="disabled"),
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- disable HSI oscillator if the node is absent (always activated by bootrom)
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and not disabled (node with status="disabled").
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Optional properties :
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a) for external oscillator: "clk-lse", "clk-hse"
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4 optional fields are managed
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- "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
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- "st,digbypass" configures the bypass mode as full-swing digital
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signal (DIGBYP)
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- "st,css" activates the clock security system (HSECSSON, LSECSSON)
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- "st,drive" (only for LSE) contains the value of the drive for the
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oscillator (see LSEDRV_ defined in the file
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dt-bindings/clock/stm32mp1-clksrc.h)
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Example board file:
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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st,bypass;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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st,css;
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st,drive = <LSEDRV_LOWEST>;
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};
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};
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b) for internal oscillator: "clk-hsi"
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Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
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In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
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doc). So this clock frequency is used to compute the expected HSI_DIV
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for the clock tree initialization.
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Example with HSIDIV = /1:
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/ {
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clocks {
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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};
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Example with HSIDIV = /2
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/ {
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clocks {
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000000>;
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};
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};
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Example of clock tree initialization
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====================================
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/ {
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clocks {
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u-boot,dm-pre-reloc;
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clk_hse: clk-hse {
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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st,digbypass;
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};
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clk_hsi: clk-hsi {
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_csi: clk-csi {
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u-boot,dm-pre-reloc;
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <4000000>;
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};
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};
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soc {
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rcc: rcc@50000000 {
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4Q
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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compatible = "st,stm32mp1-pll";
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reg = <0>;
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cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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frac = < 0x800 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
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R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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u-boot,dm-pre-reloc;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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u-boot,dm-pre-reloc;
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};
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};
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};
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};
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