u-boot/arch/riscv/cpu/generic
Bin Meng 9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12 13:21:40 +08:00
..
cpu.c common: Drop net.h from common header 2020-05-18 17:33:31 -04:00
dram.c board_f: Fix types for board_get_usable_ram_top() 2022-09-23 15:12:42 -04:00
Kconfig riscv: Rename SiFive CLINT to RISC-V ALINT 2023-07-12 13:21:40 +08:00
Makefile riscv: Rename cpu/qemu to cpu/generic 2019-02-27 09:12:33 +08:00