mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
bb597c0eeb
move CONFIG_BOOTDELAY into a Kconfig option. Used for this purpose the moveconfig.py tool in tools. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
/*
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* U-Boot - Configuration file for bf525-ucr2 board
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* The board includes ADSP-BF525 rev. 0.2,
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* 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
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* USB 2.0 High Speed OTG USB WIFI,
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* SPI flash (cFeon EN25Q128 16 MB),
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* Support PPI and ITU-R656,
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* See http://www.ucrobotics.com/?q=cn/ucr2
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*/
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#ifndef __CONFIG_BF525_UCR2_H__
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#define __CONFIG_BF525_UCR2_H__
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#include <asm/config-pre.h>
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/*
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* Processor Settings
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*/
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#define CONFIG_BFIN_CPU bf525-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
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/*
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* Clock Settings
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* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
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* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 24000000
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/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
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/* 1 = CLKIN / 2 */
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#define CONFIG_CLKIN_HALF 0
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/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
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/* 1 = bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
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/* Values can range from 0-63 (where 0 means 64) */
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#define CONFIG_VCO_MULT 20
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/* CCLK_DIV controls the core clock divider */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* SCLK_DIV controls the system clock divider */
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 4
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/*
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* Memory Settings
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*/
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#define CONFIG_MEM_ADD_WDTH 9
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#define CONFIG_MEM_SIZE 32
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/*
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* SDRAM reference page
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* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
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*/
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#define CONFIG_EBIU_SDRRC_VAL 0x3f8
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#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
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#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
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#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
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#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
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#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (320 * 1024)
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/* We don't have a parallel flash chip */
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#define CONFIG_SYS_NO_FLASH
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/* support for serial flash */
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#define CONFIG_BFIN_SPI
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#define CONFIG_SF_DEFAULT_HZ 30000000
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SPI_MAX_HZ 30000000
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#define CONFIG_ENV_OFFSET 0x10000
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#define CONFIG_ENV_SIZE 0x10000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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* Misc Settings
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*/
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BFIN_SERIAL
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
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#define CONFIG_BOOTCOMMAND "run sfboot"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"sfboot=sf probe 1;" \
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"sf read 0x1000000 0x20000 0x300000;" \
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"bootm 0x1000000\0"
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#endif
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