mirror of
https://github.com/AsahiLinux/u-boot
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395 lines
8.9 KiB
C
395 lines
8.9 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* (C) Copyright 2003 (440GX port)
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#include <asm/ppc4xx-intvec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Define the number of UIC's
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*/
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#if defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define UIC_MAX 4
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#elif defined(CONFIG_440GX) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EX)
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#define UIC_MAX 3
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#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define UIC_MAX 2
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#else
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#define UIC_MAX 1
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#endif
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/*
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* CPM interrupt vector functions.
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*/
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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int count;
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};
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static struct irq_action irq_vecs[UIC_MAX * 32];
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u32 get_dcr(u16);
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void set_dcr(u16, u32);
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#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
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static void uic_cascade_interrupt(void *para);
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#endif
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#if defined(CONFIG_440)
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/* SPRN changed in 440 */
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtspr 0x03f,%0" : : "r" (val));
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}
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#else /* !defined(CONFIG_440) */
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static __inline__ void set_pit(unsigned long val)
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{
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asm volatile("mtpit %0" : : "r" (val));
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}
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static __inline__ void set_tcr(unsigned long val)
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{
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asm volatile("mttcr %0" : : "r" (val));
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}
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtevpr %0" : : "r" (val));
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}
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#endif /* defined(CONFIG_440 */
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int interrupt_init_cpu (unsigned *decrementer_count)
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{
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int vec;
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unsigned long val;
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/* decrementer is automatically reloaded */
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*decrementer_count = 0;
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/*
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* Mark all irqs as free
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*/
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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irq_vecs[vec].count = 0;
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}
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#ifdef CONFIG_4xx
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/*
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* Init PIT
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*/
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#if defined(CONFIG_440)
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val = mfspr( tcr );
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val &= (~0x04400000); /* clear DIS & ARE */
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mtspr( tcr, val );
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mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
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mtspr( decar, 0 ); /* clear reload */
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mtspr( tsr, 0x08000000 ); /* clear DEC status */
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val = gd->bd->bi_intfreq/1000; /* 1 msec */
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mtspr( decar, val ); /* Set auto-reload value */
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mtspr( dec, val ); /* Set inital val */
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#else
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set_pit(gd->bd->bi_intfreq / 1000);
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#endif
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#endif /* CONFIG_4xx */
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#ifdef CONFIG_ADCIOP
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/*
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* Init PIT
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*/
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set_pit(66000);
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#endif
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/*
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* Enable PIT
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*/
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val = mfspr(tcr);
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val |= 0x04400000;
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mtspr(tcr, val);
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/*
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* Set EVPR to 0
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*/
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set_evpr(0x00000000);
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#if !defined(CONFIG_440GX)
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#if (UIC_MAX > 1)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0);
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#endif
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#if (UIC_MAX > 2)
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irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0);
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#endif
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#if (UIC_MAX > 3)
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irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0);
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irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0);
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#endif
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#else /* !defined(CONFIG_440GX) */
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/* Take the GX out of compatibility mode
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* Travis Sawyer, 9 Mar 2004
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* NOTE: 440gx user manual inconsistency here
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* Compatibility mode and Ethernet Clock select are not
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* correct in the manual
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*/
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mfsdr(sdr_mfr, val);
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val &= ~0x10000000;
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mtsdr(sdr_mfr,val);
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/* Enable UIC interrupts via UIC Base Enable Register */
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mtdcr(uicb0sr, UICB0_ALL);
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mtdcr(uicb0er, 0x54000000);
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/* None are critical */
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mtdcr(uicb0cr, 0);
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#endif /* !defined(CONFIG_440GX) */
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return (0);
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}
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/* Handler for UIC interrupt */
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static void uic_interrupt(u32 uic_base, int vec_base)
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{
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u32 uic_msr;
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u32 msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = get_dcr(uic_base + UIC_MSR);
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msr_shift = uic_msr;
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vec = vec_base;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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set_dcr(uic_base + UIC_ER,
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get_dcr(uic_base + UIC_ER) &
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~(0x80000000 >> (vec & 0x1f)));
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printf("Masking bogus interrupt vector %d"
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" (UIC_BASE=0x%x)\n", vec, uic_base);
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}
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/*
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* After servicing the interrupt, we have to remove the
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* status indicator
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*/
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set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f)));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#if (UIC_MAX > 1) && !defined(CONFIG_440GX)
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static void uic_cascade_interrupt(void *para)
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{
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external_interrupt(para);
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}
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#endif
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#if defined(CONFIG_440)
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#if defined(CONFIG_440GX)
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/* 440GX uses base uic register */
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#define UIC_BMSR uicb0msr
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#define UIC_BSR uicb0sr
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#else
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#define UIC_BMSR uic0msr
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#define UIC_BSR uic0sr
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#endif
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#else /* CONFIG_440 */
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#define UIC_BMSR uicmsr
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#define UIC_BSR uicsr
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#endif /* CONFIG_440 */
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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u32 uic_msr;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(UIC_BMSR);
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#if (UIC_MAX > 1)
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if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr))
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uic_interrupt(UIC1_DCR_BASE, 32);
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#endif
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#if (UIC_MAX > 2)
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if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr))
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uic_interrupt(UIC2_DCR_BASE, 64);
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#endif
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#if (UIC_MAX > 3)
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if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr))
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uic_interrupt(UIC3_DCR_BASE, 96);
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#endif
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#if defined(CONFIG_440)
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#if !defined(CONFIG_440GX)
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if (uic_msr & ~(UICB0_ALL))
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uic_interrupt(UIC0_DCR_BASE, 0);
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#else
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if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr))
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uic_interrupt(UIC0_DCR_BASE, 0);
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#endif
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#else /* CONFIG_440 */
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uic_interrupt(UIC0_DCR_BASE, 0);
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#endif /* CONFIG_440 */
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mtdcr(UIC_BSR, uic_msr);
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return;
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}
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/*
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* Install and free a interrupt handler.
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*/
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void irq_install_handler(int vec, interrupt_handler_t * handler, void *arg)
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{
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int i;
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/*
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* Print warning when replacing with a different irq vector
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*/
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if ((irq_vecs[vec].handler != NULL) && (irq_vecs[vec].handler != handler)) {
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printf("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
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vec, (uint) handler, (uint) irq_vecs[vec].handler);
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}
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irq_vecs[vec].handler = handler;
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irq_vecs[vec].arg = arg;
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i = vec & 0x1f;
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) | (0x80000000 >> i));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) | (0x80000000 >> i));
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#endif
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debug("Install interrupt for vector %d ==> %p\n", vec, handler);
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}
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void irq_free_handler (int vec)
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{
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int i;
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debug("Free interrupt for vector %d ==> %p\n",
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vec, irq_vecs[vec].handler);
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i = vec & 0x1f;
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if ((vec >= 0) && (vec < 32))
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mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
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#if (UIC_MAX > 1)
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else if ((vec >= 32) && (vec < 64))
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mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
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#endif
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#if (UIC_MAX > 2)
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else if ((vec >= 64) && (vec < 96))
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mtdcr(uic2er, mfdcr(uic2er) & ~(0x80000000 >> i));
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#endif
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#if (UIC_MAX > 3)
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else if (vec >= 96)
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mtdcr(uic3er, mfdcr(uic3er) & ~(0x80000000 >> i));
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#endif
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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}
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void timer_interrupt_cpu (struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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}
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#if defined(CONFIG_CMD_IRQ)
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int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int vec;
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printf ("Interrupt-Information:\n");
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printf ("Nr Routine Arg Count\n");
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for (vec = 0; vec < (UIC_MAX * 32); vec++) {
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if (irq_vecs[vec].handler != NULL) {
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printf ("%02d %08lx %08lx %d\n",
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vec,
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(ulong)irq_vecs[vec].handler,
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(ulong)irq_vecs[vec].arg,
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irq_vecs[vec].count);
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}
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}
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return 0;
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}
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#endif
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