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1e354cb393
This bus is used to access internal SoC PHYs. These PHYs are configured by the ENETC driver directly, but it's useful to have command line access to this MDIO to debug the system especially when using new external PHYs. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
569 lines
16 KiB
C
569 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* ENETC ethernet controller driver
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* Copyright 2017-2019 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <memalign.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <miiphy.h>
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#include "fsl_enetc.h"
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/*
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* Bind the device:
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* - set a more explicit name on the interface
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*/
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static int enetc_bind(struct udevice *dev)
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{
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char name[16];
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static int eth_num_devices;
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/*
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* prefer using PCI function numbers to number interfaces, but these
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* are only available if dts nodes are present. For PCI they are
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* optional, handle that case too. Just in case some nodes are present
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* and some are not, use different naming scheme - enetc-N based on
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* PCI function # and enetc#N based on interface count
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*/
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if (ofnode_valid(dev->node))
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sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
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else
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sprintf(name, "enetc#%u", eth_num_devices++);
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device_set_name(dev, name);
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return 0;
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}
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/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
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static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct enetc_mdio_priv priv;
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priv.regs_base = bus->priv;
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return enetc_mdio_read_priv(&priv, addr, devad, reg);
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}
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static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct enetc_mdio_priv priv;
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priv.regs_base = bus->priv;
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return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
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}
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/* only interfaces that can pin out through serdes have internal MDIO */
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static bool enetc_has_imdio(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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return !!(priv->imdio.priv);
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}
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/* set up serdes for SGMII */
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static int enetc_init_sgmii(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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bool is2500 = false;
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u16 reg;
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if (!enetc_has_imdio(dev))
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return 0;
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if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
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is2500 = true;
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/*
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* Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
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* Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
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* on PLL configuration. Setting 1G for 2.5G here is counter intuitive
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* but intentional.
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*/
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reg = ENETC_PCS_IF_MODE_SGMII;
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reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
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ENETC_PCS_IF_MODE, reg);
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/* Dev ability - SGMII */
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
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ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
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/* Adjust link timer for SGMII */
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
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ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
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ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
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reg = ENETC_PCS_CR_DEF_VAL;
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reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
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/* restart PCS AN */
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
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ENETC_PCS_CR, reg);
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return 0;
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}
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/* set up MAC for RGMII */
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static int enetc_init_rgmii(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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u32 if_mode;
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/* enable RGMII AN */
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if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
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if_mode |= ENETC_PM_IF_MODE_AN_ENA;
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enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
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return 0;
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}
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/* set up MAC and serdes for SXGMII */
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static int enetc_init_sxgmii(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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u32 if_mode;
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/* set ifmode to (US)XGMII */
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if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
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if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
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enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
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if (!enetc_has_imdio(dev))
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return 0;
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/* Dev ability - SXGMII */
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
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ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
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/* Restart PCS AN */
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enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
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ENETC_PCS_CR,
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ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
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return 0;
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}
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/* Apply protocol specific configuration to MAC, serdes as needed */
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static void enetc_start_pcs(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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const char *if_str;
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priv->if_type = PHY_INTERFACE_MODE_NONE;
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/* register internal MDIO for debug purposes */
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if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
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priv->imdio.read = enetc_mdio_read;
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priv->imdio.write = enetc_mdio_write;
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priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
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strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
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if (!miiphy_get_dev_by_name(priv->imdio.name))
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mdio_register(&priv->imdio);
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}
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if (!ofnode_valid(dev->node)) {
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enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
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return;
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}
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if_str = ofnode_read_string(dev->node, "phy-mode");
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if (if_str)
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priv->if_type = phy_get_interface_by_name(if_str);
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else
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enetc_dbg(dev,
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"phy-mode property not found, defaulting to SGMII\n");
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if (priv->if_type < 0)
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priv->if_type = PHY_INTERFACE_MODE_NONE;
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switch (priv->if_type) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_SGMII_2500:
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enetc_init_sgmii(dev);
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break;
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case PHY_INTERFACE_MODE_XGMII:
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_XFI:
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enetc_init_sxgmii(dev);
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break;
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};
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}
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/* Configure the actual/external ethernet PHY, if one is found */
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static void enetc_config_phy(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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int supported;
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priv->phy = dm_eth_phy_connect(dev);
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if (!priv->phy)
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return;
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supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
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priv->phy->supported &= supported;
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priv->phy->advertising &= supported;
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phy_config(priv->phy);
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}
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/*
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* Probe ENETC driver:
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* - initialize port and station interface BARs
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*/
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static int enetc_probe(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
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enetc_dbg(dev, "interface disabled\n");
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return -ENODEV;
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}
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priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
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sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
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priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
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sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
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if (!priv->enetc_txbd || !priv->enetc_rxbd) {
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/* free should be able to handle NULL, just free all pointers */
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free(priv->enetc_txbd);
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free(priv->enetc_rxbd);
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return -ENOMEM;
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}
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/* initialize register */
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priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
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if (!priv->regs_base) {
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enetc_dbg(dev, "failed to map BAR0\n");
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return -EINVAL;
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}
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priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
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dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
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enetc_start_pcs(dev);
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enetc_config_phy(dev);
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return 0;
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}
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/*
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* Remove the driver from an interface:
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* - free up allocated memory
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*/
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static int enetc_remove(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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free(priv->enetc_txbd);
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free(priv->enetc_rxbd);
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return 0;
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}
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/* ENETC Port MAC address registers, accepts big-endian format */
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static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
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{
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u16 lower = *(const u16 *)(addr + 4);
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u32 upper = *(const u32 *)addr;
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enetc_write_port(priv, ENETC_PSIPMAR0, upper);
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enetc_write_port(priv, ENETC_PSIPMAR1, lower);
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}
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/* Configure port parameters (# of rings, frame size, enable port) */
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static void enetc_enable_si_port(struct enetc_priv *priv)
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{
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u32 val;
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/* set Rx/Tx BDR count */
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val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
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val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
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enetc_write_port(priv, ENETC_PSICFGR(0), val);
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/* set Rx max frame size */
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enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
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/* enable MAC port */
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enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
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/* enable port */
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enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
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/* set SI cache policy */
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enetc_write(priv, ENETC_SICAR0,
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ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
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/* enable SI */
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enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
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}
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/* returns DMA address for a given buffer index */
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static inline u64 enetc_rxb_address(struct udevice *dev, int i)
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{
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return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
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}
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/*
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* Setup a single Tx BD Ring (ID = 0):
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* - set Tx buffer descriptor address
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* - set the BD count
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* - initialize the producer and consumer index
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*/
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static void enetc_setup_tx_bdr(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *tx_bdr = &priv->tx_bdr;
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u64 tx_bd_add = (u64)priv->enetc_txbd;
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/* used later to advance to the next Tx BD */
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tx_bdr->bd_count = ENETC_BD_CNT;
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tx_bdr->next_prod_idx = 0;
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tx_bdr->next_cons_idx = 0;
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tx_bdr->cons_idx = priv->regs_base +
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ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
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tx_bdr->prod_idx = priv->regs_base +
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ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
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/* set Tx BD address */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
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lower_32_bits(tx_bd_add));
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
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upper_32_bits(tx_bd_add));
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/* set Tx 8 BD count */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
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tx_bdr->bd_count);
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/* reset both producer/consumer indexes */
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enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
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enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
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/* enable TX ring */
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enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
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}
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/*
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* Setup a single Rx BD Ring (ID = 0):
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* - set Rx buffer descriptors address (one descriptor per buffer)
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* - set buffer size as max frame size
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* - enable Rx ring
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* - reset consumer and producer indexes
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* - set buffer for each descriptor
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*/
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static void enetc_setup_rx_bdr(struct udevice *dev)
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{
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struct enetc_priv *priv = dev_get_priv(dev);
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struct bd_ring *rx_bdr = &priv->rx_bdr;
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u64 rx_bd_add = (u64)priv->enetc_rxbd;
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int i;
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/* used later to advance to the next BD produced by ENETC HW */
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rx_bdr->bd_count = ENETC_BD_CNT;
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rx_bdr->next_prod_idx = 0;
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rx_bdr->next_cons_idx = 0;
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rx_bdr->cons_idx = priv->regs_base +
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ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
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rx_bdr->prod_idx = priv->regs_base +
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ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
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/* set Rx BD address */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
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lower_32_bits(rx_bd_add));
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
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upper_32_bits(rx_bd_add));
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/* set Rx BD count (multiple of 8) */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
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rx_bdr->bd_count);
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/* set Rx buffer size */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
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/* fill Rx BD */
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memset(priv->enetc_rxbd, 0,
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rx_bdr->bd_count * sizeof(union enetc_rx_bd));
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for (i = 0; i < rx_bdr->bd_count; i++) {
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priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
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/* each RX buffer must be aligned to 64B */
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WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
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}
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/* reset producer (ENETC owned) and consumer (SW owned) index */
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enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
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enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
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/* enable Rx ring */
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enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
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}
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/*
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* Start ENETC interface:
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* - perform FLR
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* - enable access to port and SI registers
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* - set mac address
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* - setup TX/RX buffer descriptors
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* - enable Tx/Rx rings
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*/
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static int enetc_start(struct udevice *dev)
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{
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struct eth_pdata *plat = dev_get_platdata(dev);
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struct enetc_priv *priv = dev_get_priv(dev);
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/* reset and enable the PCI device */
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dm_pci_flr(dev);
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dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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if (!is_valid_ethaddr(plat->enetaddr)) {
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enetc_dbg(dev, "invalid MAC address, generate random ...\n");
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net_random_ethaddr(plat->enetaddr);
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}
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enetc_set_primary_mac_addr(priv, plat->enetaddr);
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enetc_enable_si_port(priv);
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/* setup Tx/Rx buffer descriptors */
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enetc_setup_tx_bdr(dev);
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enetc_setup_rx_bdr(dev);
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if (priv->if_type == PHY_INTERFACE_MODE_RGMII ||
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priv->if_type == PHY_INTERFACE_MODE_RGMII_ID ||
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priv->if_type == PHY_INTERFACE_MODE_RGMII_RXID ||
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priv->if_type == PHY_INTERFACE_MODE_RGMII_TXID)
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enetc_init_rgmii(dev);
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if (priv->phy)
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phy_startup(priv->phy);
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return 0;
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}
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/*
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* Stop the network interface:
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* - just quiesce it, we can wipe all configuration as _start starts from
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* scratch each time
|
|
*/
|
|
static void enetc_stop(struct udevice *dev)
|
|
{
|
|
/* FLR is sufficient to quiesce the device */
|
|
dm_pci_flr(dev);
|
|
/* leave the BARs accessible after we stop, this is needed to use
|
|
* internal MDIO in command line.
|
|
*/
|
|
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
|
|
}
|
|
|
|
/*
|
|
* ENETC transmit packet:
|
|
* - check if Tx BD ring is full
|
|
* - set buffer/packet address (dma address)
|
|
* - set final fragment flag
|
|
* - try while producer index equals consumer index or timeout
|
|
*/
|
|
static int enetc_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct enetc_priv *priv = dev_get_priv(dev);
|
|
struct bd_ring *txr = &priv->tx_bdr;
|
|
void *nv_packet = (void *)packet;
|
|
int tries = ENETC_POLL_TRIES;
|
|
u32 pi, ci;
|
|
|
|
pi = txr->next_prod_idx;
|
|
ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
|
|
/* Tx ring is full when */
|
|
if (((pi + 1) % txr->bd_count) == ci) {
|
|
enetc_dbg(dev, "Tx BDR full\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
|
|
upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
|
|
|
|
/* prepare Tx BD */
|
|
memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
|
|
priv->enetc_txbd[pi].addr =
|
|
cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
|
|
priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
|
|
priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
|
|
priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
|
|
dmb();
|
|
/* send frame: increment producer index */
|
|
pi = (pi + 1) % txr->bd_count;
|
|
txr->next_prod_idx = pi;
|
|
enetc_write_reg(txr->prod_idx, pi);
|
|
while ((--tries >= 0) &&
|
|
(pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
|
|
udelay(10);
|
|
|
|
return tries > 0 ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
/*
|
|
* Receive frame:
|
|
* - wait for the next BD to get ready bit set
|
|
* - clean up the descriptor
|
|
* - move on and indicate to HW that the cleaned BD is available for Rx
|
|
*/
|
|
static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct enetc_priv *priv = dev_get_priv(dev);
|
|
struct bd_ring *rxr = &priv->rx_bdr;
|
|
int tries = ENETC_POLL_TRIES;
|
|
int pi = rxr->next_prod_idx;
|
|
int ci = rxr->next_cons_idx;
|
|
u32 status;
|
|
int len;
|
|
u8 rdy;
|
|
|
|
do {
|
|
dmb();
|
|
status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
|
|
/* check if current BD is ready to be consumed */
|
|
rdy = ENETC_RXBD_STATUS_R(status);
|
|
} while (--tries >= 0 && !rdy);
|
|
|
|
if (!rdy)
|
|
return -EAGAIN;
|
|
|
|
dmb();
|
|
len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
|
|
*packetp = (uchar *)enetc_rxb_address(dev, pi);
|
|
enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
|
|
ENETC_RXBD_STATUS_ERRORS(status),
|
|
upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
|
|
|
|
/* BD clean up and advance to next in ring */
|
|
memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
|
|
priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
|
|
rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
|
|
ci = (ci + 1) % rxr->bd_count;
|
|
rxr->next_cons_idx = ci;
|
|
dmb();
|
|
/* free up the slot in the ring for HW */
|
|
enetc_write_reg(rxr->cons_idx, ci);
|
|
|
|
return len;
|
|
}
|
|
|
|
static const struct eth_ops enetc_ops = {
|
|
.start = enetc_start,
|
|
.send = enetc_send,
|
|
.recv = enetc_recv,
|
|
.stop = enetc_stop,
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_enetc) = {
|
|
.name = "enetc_eth",
|
|
.id = UCLASS_ETH,
|
|
.bind = enetc_bind,
|
|
.probe = enetc_probe,
|
|
.remove = enetc_remove,
|
|
.ops = &enetc_ops,
|
|
.priv_auto_alloc_size = sizeof(struct enetc_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|
|
|
|
static struct pci_device_id enetc_ids[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
|