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3c2bbd5886
The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399 in a Qseven-compatible form-factor. These changes add a device-tree describing the board and its interfaces for basic functionality (e.g. GbE, SPI, eMMC, SD-card). This includes the following changes from the original development: * dts: rk3399-puma: include DTS for RK3399-Q7 SoM in the Makefile * dts: rk3399-puma: add gmac for the RK3399-Q7 This change enables the Gigabit Ethernet support on the RK3399-Q7. * dts: rk3399-puma: use serial0 for stdout * dts: rk3399-puma: prepare the sdmmc node for SPL booting * dts: rk3399-puma: enable spi1 and spi5, add /spi1/spiflash The RK3399-Q7 (Puma) unsually (this is a build-time option for customised boards) has an on-module SPI-flash connected to SPI1. As of today, this is a Winbond W25Q32DW (32MBit) device. The SPI5 controller is routed to the Q7 edge connector and provides general-purpose SPI connectivity for customer base-boards. With some minor improvements on integration into our outbound tree - explicitly modelled the SPI flash as 'spiflash' under spi0 [dts: rk3399-puma: explicitly model spi-flash under spi1] - renamed the aliases to spi0 and spi1 to allow easier use of commands and legacy (SPL) infrastructure... i.e. the controllers will be 0 and 1 for 'sf probe', 'sspi', etc. [dts: rk3399-puma: rename aliases to number spi as 0 and 1 for commands] * dts: rk3399-puma: include SPI in the spl-boot-order property Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org>
189 lines
3 KiB
Text
189 lines
3 KiB
Text
/*
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/pwm/pwm.h>
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#include "rk3399.dtsi"
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#include "rk3399-sdram-ddr3-1333.dtsi"
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/ {
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model = "Theobroma Systems RK3399-Q7 SoM";
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compatible = "tsd,puma", "rockchip,rk3399";
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chosen {
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stdout-path = "serial0:115200n8";
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u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc;
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};
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aliases {
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spi0 = &spi1;
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spi1 = &spi5;
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};
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vdd_center: vdd-center {
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compatible = "pwm-regulator";
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pwms = <&pwm3 0 25000 0>;
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regulator-name = "vdd_center";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-init-microvolt = <950000>;
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regulator-always-on;
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regulator-boot-on;
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status = "okay";
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};
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vcc3v3_sys: vcc3v3-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_phy";
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regulator-always-on;
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regulator-boot-on;
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};
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vcc5v0_host: vcc5v0-host-en {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_host";
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gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
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};
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clkin_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clkin_gmac";
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#clock-cells = <0>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_phy";
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&emmc_phy {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&pwm2 {
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status = "okay";
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};
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&pwm3 {
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status = "okay";
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};
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&sdmmc {
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u-boot,dm-pre-reloc;
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bus-width = <4>;
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fifo-mode; /* until we fix DMA in SPL */
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status = "okay";
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};
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&sdhci {
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bus-width = <8>;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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non-removable;
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&dwc3_typec0 {
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status = "okay";
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&usb_host1_ohci {
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status = "okay";
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};
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&dwc3_typec1 {
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status = "okay";
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};
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&pinctrl {
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pmic {
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pmic_int_l: pmic-int-l {
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rockchip,pins =
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<1 21 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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pmic_dvs2: pmic-dvs2 {
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rockchip,pins =
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<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&gmac {
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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assigned-clocks = <&cru SCLK_RMII_SRC>;
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assigned-clock-parents = <&clkin_gmac>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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tx_delay = <0x10>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&spi1 {
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u-boot,dm-pre-reloc;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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spiflash: w25q32dw@0 {
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u-boot,dm-pre-reloc;
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compatible = "spi-flash";
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reg = <0>;
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spi-max-frequency = <5000000>;
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spi-cpol;
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spi-cpha;
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};
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};
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&spi5 {
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status = "okay";
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};
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