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u-boot/board/freescale/p1_p2_rdb_pc
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Tom Rini 5b8031ccb4 Add more SPDX-License-Identifier tags 
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
..
ddr.c Add more SPDX-License-Identifier tags 2016-01-19 08:31:21 -05:00
Kconfig kconfig: remove redundant "string" type in arch and board Kconfigs 2014-09-13 16:43:55 -04:00
law.c Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
MAINTAINERS MAINTAINERS: comment out blank M: field 2014-09-24 18:30:28 -04:00
Makefile freescale: p1_p2_rdb_pc: rename COBJS-y to obj-y 2013-11-06 08:50:28 -05:00
p1_p2_rdb_pc.c powerpc/p2020rdb: fix the FDT_ERR_NOTFOUND issue 2015-07-28 14:41:15 -07:00
README p1020rdb-pd: platform support 2013-08-09 12:41:40 -07:00
spl.c Move console definitions into a new console.h file 2015-11-19 20:27:50 -07:00
spl_minimal.c Driver/DDR: Moving Freescale DDR driver to a common driver 2013-11-25 11:43:43 -08:00
tlb.c powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand boot 2013-10-16 16:13:12 -07:00

README 

Overview
--------
P1_P2_RDB_PC represents a set of boards including
    P1020MSBG-PC
    P1020RDB-PC
    P1020RDB-PD
    P1020UTM-PC
    P1021RDB-PC
    P1024RDB
    P1025RDB
    P2020RDB-PC

They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
has 64-bit DDR. All others have 32-bit DDR.

Key features on these boards include:
    * DDR3
    * NOR flash
    * NAND flash (on RDB's only)
    * SPI flash (on RDB's only)
    * SDHC/MMC card slot
    * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
    * PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported with
this approach. ODT option is forced to fit this set of boards, again because
they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
pins multiplexing. QE function needs to be disabled to access Nor Flash and
CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.