mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
9eae844125
This patch will fix these checkpatch issues. ERROR: spaces required around that '==' (ctx:VxV) +#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ ERROR: spaces required around that '==' (ctx:VxV) +#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ ERROR: spaces required around that '==' (ctx:VxV) +#if USB_CLOCK==0 ERROR: spaces required around that '==' (ctx:VxV) +#elif USB_CLOCK==1 CHECK: spaces required around that ':' (ctx:VxV) + "bne 1b":"=r" (loops):"0" (loops)); Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
139 lines
2.9 KiB
C
139 lines
2.9 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002, 2010
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FCLK_SPEED 1
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#if (FCLK_SPEED == 0) /* Fout = 203MHz, Fin = 12MHz for Audio */
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#define M_MDIV 0xC3
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#define M_PDIV 0x4
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#define M_SDIV 0x1
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#elif (FCLK_SPEED == 1) /* Fout = 202.8MHz */
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#define M_MDIV 0xA1
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#define M_PDIV 0x3
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#define M_SDIV 0x1
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#endif
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#define USB_CLOCK 1
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#if (USB_CLOCK == 0)
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#define U_M_MDIV 0xA1
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x1
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#elif (USB_CLOCK == 1)
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#define U_M_MDIV 0x48
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#define U_M_PDIV 0x3
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#define U_M_SDIV 0x2
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#endif
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static inline void pll_delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_early_init_f(void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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writel(0xFFFFFF, &clk_power->locktime);
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/* configure MPLL */
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writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
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&clk_power->mpllcon);
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/* some delay between MPLL and UPLL */
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pll_delay(4000);
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/* configure UPLL */
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writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
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&clk_power->upllcon);
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/* some delay between MPLL and UPLL */
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pll_delay(8000);
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/* set up the I/O ports */
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writel(0x007FFFFF, &gpio->gpacon);
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writel(0x00044555, &gpio->gpbcon);
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writel(0x000007FF, &gpio->gpbup);
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writel(0xAAAAAAAA, &gpio->gpccon);
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writel(0x0000FFFF, &gpio->gpcup);
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writel(0xAAAAAAAA, &gpio->gpdcon);
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writel(0x0000FFFF, &gpio->gpdup);
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writel(0xAAAAAAAA, &gpio->gpecon);
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writel(0x0000FFFF, &gpio->gpeup);
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writel(0x000055AA, &gpio->gpfcon);
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writel(0x000000FF, &gpio->gpfup);
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writel(0xFF95FFBA, &gpio->gpgcon);
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writel(0x0000FFFF, &gpio->gpgup);
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writel(0x002AFAAA, &gpio->gphcon);
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writel(0x000007FF, &gpio->gphup);
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return 0;
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}
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int board_init(void)
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{
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/* arch number of SMDK2410-Board */
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gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0x30000100;
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icache_enable();
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dcache_enable();
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return 0;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_CS8900
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
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#endif
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return rc;
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}
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#endif
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/*
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* Hardcoded flash setup:
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* Flash 0 is a non-CFI AMD AM29LV800BB flash.
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*/
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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info->portwidth = FLASH_CFI_16BIT;
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info->chipwidth = FLASH_CFI_BY16;
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info->interface = FLASH_CFI_X16;
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return 1;
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}
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