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https://github.com/AsahiLinux/u-boot
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c7554574ff
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
105 lines
2.3 KiB
C
105 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _CLK_NPCM_H_
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#define _CLK_NPCM_H_
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#include <clk-uclass.h>
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/* Register offsets */
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#define CLKSEL 0x04 /* clock source selection */
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#define CLKDIV1 0x08 /* clock divider 1 */
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#define CLKDIV2 0x2C /* clock divider 2 */
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#define CLKDIV3 0x58 /* clock divider 3 */
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#define PLLCON0 0x0C /* pll0 control */
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#define PLLCON1 0x10 /* pll1 control */
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#define PLLCON2 0x54 /* pll2 control */
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/* CLKSEL bit filed */
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#define NPCM7XX_CPUCKSEL GENMASK(1, 0)
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#define NPCM8XX_CPUCKSEL GENMASK(2, 0)
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#define SDCKSEL GENMASK(7, 6)
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#define UARTCKSEL GENMASK(9, 8)
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#define TIMCKSEL GENMASK(15, 14)
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/* CLKDIV1 bit filed */
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#define SPI3CKDIV GENMASK(10, 6)
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#define MMCCKDIV GENMASK(15, 11)
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#define UARTDIV1 GENMASK(20, 16)
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#define TIMCKDIV GENMASK(25, 21)
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#define CLK4DIV GENMASK(27, 26)
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/* CLKDIV2 bit filed */
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#define APB5CKDIV GENMASK(23, 22)
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#define APB2CKDIV GENMASK(27, 26)
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/* CLKDIV3 bit filed */
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#define SPIXCKDIV GENMASK(5, 1)
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#define SPI0CKDIV GENMASK(10, 6)
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#define UARTDIV2 GENMASK(15, 11)
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#define SPI1CKDIV GENMASK(23, 16)
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/* PLLCON bit filed */
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#define PLLCON_INDV GENMASK(5, 0)
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#define PLLCON_OTDV1 GENMASK(10, 8)
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#define PLLCON_OTDV2 GENMASK(15, 13)
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#define PLLCON_FBDV GENMASK(27, 16)
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/* Flags */
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#define DIV_TYPE1 BIT(0) /* div = clkdiv + 1 */
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#define DIV_TYPE2 BIT(1) /* div = 1 << clkdiv */
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#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
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#define POST_DIV2 BIT(3) /* Post divisor = 2 */
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#define FIXED_PARENT BIT(4) /* clock source is fixed */
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/* Parameters of PLL configuration */
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struct npcm_clk_pll {
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const int id;
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const int parent_id;
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u32 reg;
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u32 flags;
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};
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/* Parent clock id to clksel mapping */
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struct parent_data {
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int id;
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int clksel;
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};
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/* Parameters of parent selection */
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struct npcm_clk_select {
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const int id;
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const struct parent_data *parents;
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u32 reg;
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u32 mask;
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u8 num_parents;
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u32 flags;
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};
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/* Parameters of clock divider */
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struct npcm_clk_div {
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const int id;
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u32 reg;
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u32 mask;
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u32 flags;
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};
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struct npcm_clk_data {
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struct npcm_clk_pll *clk_plls;
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int num_plls;
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struct npcm_clk_select *clk_selectors;
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int num_selectors;
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struct npcm_clk_div *clk_dividers;
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int num_dividers;
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int refclk_id;
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int pll0_id;
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};
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struct npcm_clk_priv {
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void __iomem *base;
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struct npcm_clk_data *clk_data;
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int num_clks;
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};
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extern const struct clk_ops npcm_clk_ops;
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#endif
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