mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
402 lines
8.8 KiB
C
402 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*
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* Peng Fan <peng.fan@nxp.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/hab.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/syscounter.h>
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#include <asm/armv8/mmu.h>
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#include <dm/uclass.h>
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#include <errno.h>
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#include <fdt_support.h>
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#include <fsl_wdog.h>
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#include <imx_sip.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_IMX_HAB)
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struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
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.bank = 1,
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.word = 3,
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};
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#endif
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int timer_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
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unsigned long freq = readl(&sctr->cntfid0);
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/* Update with accurate clock frequency */
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asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
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clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
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SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
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#endif
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gd->arch.tbl = 0;
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gd->arch.tbu = 0;
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return 0;
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}
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void enable_tzc380(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable TZASC and lock setting */
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setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
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setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
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if (is_imx8mm() || is_imx8mn())
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setbits_le32(&gpr->gpr[10], BIT(1));
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/*
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* set Region 0 attribute to allow secure and non-secure
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* read/write permission. Found some masters like usb dwc3
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* controllers can't work with secure memory.
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*/
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writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
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}
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void set_wdog_reset(struct wdog_regs *wdog)
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{
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/*
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* Output WDOG_B signal to reset external pmic or POR_B decided by
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* the board design. Without external reset, the peripherals/DDR/
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* PMIC are not reset, that may cause system working abnormal.
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* WDZST bit is write-once only bit. Align this bit in kernel,
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* otherwise kernel code will have no chance to set this bit.
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*/
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setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
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}
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static struct mm_region imx8m_mem_map[] = {
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{
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/* ROM */
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* CAAM */
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.virt = 0x100000UL,
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.phys = 0x100000UL,
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.size = 0x8000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* TCM */
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.virt = 0x7C0000UL,
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.phys = 0x7C0000UL,
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.size = 0x80000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OCRAM */
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.virt = 0x900000UL,
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.phys = 0x900000UL,
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.size = 0x200000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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}, {
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/* AIPS */
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.virt = 0xB00000UL,
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.phys = 0xB00000UL,
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.size = 0x3f500000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* DRAM1 */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = PHYS_SDRAM_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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#ifdef PHYS_SDRAM_2_SIZE
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}, {
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/* DRAM2 */
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.virt = 0x100000000UL,
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.phys = 0x100000000UL,
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.size = PHYS_SDRAM_2_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_OUTER_SHARE
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#endif
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = imx8m_mem_map;
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void enable_caches(void)
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{
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/*
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* If OPTEE runs, remove OPTEE memory from MMU table to
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* avoid speculative prefetch. OPTEE runs at the top of
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* the first memory bank
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*/
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if (rom_pointer[1])
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imx8m_mem_map[5].size -= rom_pointer[1];
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icache_enable();
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dcache_enable();
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}
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static u32 get_cpu_variant_type(u32 type)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[1];
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struct fuse_bank1_regs *fuse =
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(struct fuse_bank1_regs *)bank->fuse_regs;
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u32 value = readl(&fuse->tester4);
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if (type == MXC_CPU_IMX8MM) {
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switch (value & 0x3) {
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case 2:
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if (value & 0x1c0000)
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return MXC_CPU_IMX8MMDL;
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else
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return MXC_CPU_IMX8MMD;
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case 3:
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if (value & 0x1c0000)
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return MXC_CPU_IMX8MMSL;
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else
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return MXC_CPU_IMX8MMS;
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default:
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if (value & 0x1c0000)
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return MXC_CPU_IMX8MML;
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break;
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}
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}
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return type;
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}
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u32 get_cpu_rev(void)
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{
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struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
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u32 reg = readl(&ana_pll->digprog);
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u32 type = (reg >> 16) & 0xff;
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u32 major_low = (reg >> 8) & 0xff;
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u32 rom_version;
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reg &= 0xff;
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/* iMX8MP */
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if (major_low == 0x43) {
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return (MXC_CPU_IMX8MP << 12) | reg;
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} else if (major_low == 0x42) {
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/* iMX8MN */
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return (MXC_CPU_IMX8MN << 12) | reg;
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} else if (major_low == 0x41) {
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type = get_cpu_variant_type(MXC_CPU_IMX8MM);
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} else {
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if (reg == CHIP_REV_1_0) {
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/*
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* For B0 chip, the DIGPROG is not updated,
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* it is still TO1.0. we have to check ROM
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* version or OCOTP_READ_FUSE_DATA.
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* 0xff0055aa is magic number for B1.
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*/
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if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
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reg = CHIP_REV_2_1;
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} else {
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rom_version =
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readl((void __iomem *)ROM_VERSION_A0);
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if (rom_version != CHIP_REV_1_0) {
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rom_version = readl((void __iomem *)ROM_VERSION_B0);
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rom_version &= 0xff;
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if (rom_version == CHIP_REV_2_0)
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reg = CHIP_REV_2_0;
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}
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}
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}
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}
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return (type << 12) | reg;
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}
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static void imx_set_wdog_powerdown(bool enable)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
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/* Write to the PDE (Power Down Enable) bit */
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writew(enable, &wdog1->wmcr);
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writew(enable, &wdog2->wmcr);
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writew(enable, &wdog3->wmcr);
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}
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int arch_cpu_init_dm(void)
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{
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struct udevice *dev;
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int ret;
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if (CONFIG_IS_ENABLED(CLK)) {
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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return ret;
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}
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}
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return 0;
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}
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int arch_cpu_init(void)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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/*
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* ROM might disable clock for SCTR,
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* enable the clock before timer_init.
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*/
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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clock_enable(CCGR_SCTR, 1);
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/*
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* Init timer at very early state, because sscg pll setting
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* will use it
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*/
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timer_init();
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if (IS_ENABLED(CONFIG_SPL_BUILD)) {
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clock_init();
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imx_set_wdog_powerdown(false);
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}
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if (is_imx8mq()) {
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clock_enable(CCGR_OCOTP, 1);
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if (readl(&ocotp->ctrl) & 0x200)
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writel(0x200, &ocotp->ctrl_clr);
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}
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return 0;
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}
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#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
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struct rom_api *g_rom_api = (struct rom_api *)0x980;
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enum boot_device get_boot_device(void)
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{
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volatile gd_t *pgd = gd;
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int ret;
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u32 boot;
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u16 boot_type;
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u8 boot_instance;
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enum boot_device boot_dev = SD1_BOOT;
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ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
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((uintptr_t)&boot) ^ QUERY_BT_DEV);
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gd = pgd;
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if (ret != ROM_API_OKAY) {
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puts("ROMAPI: failure at query_boot_info\n");
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return -1;
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}
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boot_type = boot >> 16;
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boot_instance = (boot >> 8) & 0xff;
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switch (boot_type) {
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case BT_DEV_TYPE_SD:
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boot_dev = boot_instance + SD1_BOOT;
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break;
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case BT_DEV_TYPE_MMC:
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boot_dev = boot_instance + MMC1_BOOT;
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break;
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case BT_DEV_TYPE_NAND:
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boot_dev = NAND_BOOT;
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break;
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case BT_DEV_TYPE_FLEXSPINOR:
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boot_dev = QSPI_BOOT;
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break;
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case BT_DEV_TYPE_USB:
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boot_dev = USB_BOOT;
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break;
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default:
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break;
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}
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return boot_dev;
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}
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#endif
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bool is_usb_boot(void)
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{
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return get_boot_device() == USB_BOOT;
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}
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#ifdef CONFIG_OF_SYSTEM_SETUP
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int ft_system_setup(void *blob, bd_t *bd)
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{
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int i = 0;
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int rc;
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int nodeoff;
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/* Disable the CPU idle for A0 chip since the HW does not support it */
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if (is_soc_rev(CHIP_REV_1_0)) {
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static const char * const nodes_path[] = {
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"/cpus/cpu@0",
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"/cpus/cpu@1",
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"/cpus/cpu@2",
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"/cpus/cpu@3",
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};
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for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
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nodeoff = fdt_path_offset(blob, nodes_path[i]);
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if (nodeoff < 0)
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continue; /* Not found, skip it */
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printf("Found %s node\n", nodes_path[i]);
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rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
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if (rc) {
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printf("Unable to update property %s:%s, err=%s\n",
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nodes_path[i], "status", fdt_strerror(rc));
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return rc;
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}
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printf("Remove %s:%s\n", nodes_path[i],
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"cpu-idle-states");
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}
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET)
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void reset_cpu(ulong addr)
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{
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struct watchdog_regs *wdog = (struct watchdog_regs *)addr;
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if (!addr)
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wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
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/* Clear WDA to trigger WDOG_B immediately */
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writew((WCR_WDE | WCR_SRS), &wdog->wcr);
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while (1) {
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/*
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* spin for .5 seconds before reset
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*/
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}
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}
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#endif
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