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https://github.com/AsahiLinux/u-boot
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b630d57d0a
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Simon Glass <sjg@chromium.org>
74 lines
1.6 KiB
C
74 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Author: Anup Patel <anup.patel@wdc.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <div64.h>
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#include <dm.h>
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struct clk_fixed_factor {
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struct clk parent;
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unsigned int div;
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unsigned int mult;
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};
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#define to_clk_fixed_factor(dev) \
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((struct clk_fixed_factor *)dev_get_platdata(dev))
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static ulong clk_fixed_factor_get_rate(struct clk *clk)
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{
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uint64_t rate;
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struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
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if (clk->id != 0)
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return -EINVAL;
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rate = clk_get_rate(&ff->parent);
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if (IS_ERR_VALUE(rate))
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return rate;
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do_div(rate, ff->div);
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return rate * ff->mult;
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}
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const struct clk_ops clk_fixed_factor_ops = {
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.get_rate = clk_fixed_factor_get_rate,
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};
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static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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int err;
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struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
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err = clk_get_by_index(dev, 0, &ff->parent);
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if (err)
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return err;
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ff->div = dev_read_u32_default(dev, "clock-div", 1);
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ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
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#endif
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return 0;
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}
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static const struct udevice_id clk_fixed_factor_match[] = {
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{
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.compatible = "fixed-factor-clock",
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},
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(clk_fixed_factor) = {
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.name = "fixed_factor_clock",
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.id = UCLASS_CLK,
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.of_match = clk_fixed_factor_match,
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.ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
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.ops = &clk_fixed_factor_ops,
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};
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