mirror of
https://github.com/AsahiLinux/u-boot
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623a8c812e
LG X3 is a development board based on Nvidia Tegra 3 SoC on base of which Optimus 4X HD and Optimus Vu were created. Both smartphones feature a 4.7" and 5" panels respectively, an Nvidia Tegra 3 quad-core chip, 1 GB of RAM and 16/32 GB of internal storage. Optimux 4X HD additionally has a micro SD slot. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # LG P880 T30 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
176 lines
4.1 KiB
C
176 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* (C) Copyright 2022
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <log.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/fuse.h>
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#include <asm/gpio.h>
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#include <linux/delay.h>
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#include "pinmux-config-x3.h"
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#define MAX77663_I2C_ADDR 0x1C
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#define MAX77663_REG_SD2 0x18
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#define MAX77663_REG_LDO2 0x27
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#define MAX77663_REG_LDO3 0x29
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#define MAX77663_REG_LDO5 0x2D
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#define MAX77663_REG_ONOFF_CFG1 0x41
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#define ONOFF_PWR_OFF BIT(1)
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#ifdef CONFIG_CMD_POWEROFF
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int do_poweroff(struct cmd_tbl *cmdtp, int flag,
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int argc, char *const argv[])
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{
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struct udevice *dev;
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uchar data_buffer[1];
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int ret;
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ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
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if (ret) {
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log_debug("cannot find PMIC I2C chip\n");
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return 0;
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}
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ret = dm_i2c_read(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
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if (ret)
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return ret;
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data_buffer[0] |= ONOFF_PWR_OFF;
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ret = dm_i2c_write(dev, MAX77663_REG_ONOFF_CFG1, data_buffer, 1);
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if (ret)
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return ret;
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/* wait some time and then print error */
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mdelay(5000);
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printf("Failed to power off!!!\n");
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return 1;
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}
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#endif
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_pingrp_table(tegra3_x3_pinmux_common,
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ARRAY_SIZE(tegra3_x3_pinmux_common));
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#ifdef CONFIG_DEVICE_P880
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pinmux_config_pingrp_table(tegra3_p880_pinmux,
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ARRAY_SIZE(tegra3_p880_pinmux));
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#endif
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#ifdef CONFIG_DEVICE_P895
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pinmux_config_pingrp_table(tegra3_p895_pinmux,
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ARRAY_SIZE(tegra3_p895_pinmux));
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#endif
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}
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#ifdef CONFIG_MMC_SDHCI_TEGRA
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static void max77663_voltage_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = i2c_get_chip_for_busnum(0, MAX77663_I2C_ADDR, 1, &dev);
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if (ret) {
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log_debug("cannot find PMIC I2C chip\n");
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return;
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}
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/* 0x60 for 1.8v, bit7:0 = voltage */
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ret = dm_i2c_reg_write(dev, MAX77663_REG_SD2, 0x60);
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if (ret)
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log_debug("vdd_1v8_vio set failed: %d\n", ret);
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/* 0xF2 for 3.30v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO2, 0xF2);
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if (ret)
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log_debug("avdd_usb set failed: %d\n", ret);
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/* 0xEC for 3.00v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO3, 0xEC);
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if (ret)
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log_debug("vdd_usd set failed: %d\n", ret);
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/* 0xE9 for 2.85v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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ret = dm_i2c_reg_write(dev, MAX77663_REG_LDO5, 0xE9);
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if (ret)
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log_debug("vcore_emmc set failed: %d\n", ret);
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}
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/*
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* Routine: pin_mux_mmc
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* Description: setup the MMC muxes, power rails, etc.
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*/
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void pin_mux_mmc(void)
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{
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/* Bring up uSD and eMMC power */
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max77663_voltage_init();
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}
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#endif /* MMC */
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int nvidia_board_init(void)
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{
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/* Set up panel bridge clocks */
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clock_start_periph_pll(PERIPH_ID_EXTPERIPH3, CLOCK_ID_PERIPH,
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24 * 1000000);
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clock_external_output(3);
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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/* First 3 bytes refer to LG vendor */
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u8 btmacaddr[6] = { 0x00, 0x00, 0x00, 0xD0, 0xC9, 0x88 };
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/* Generate device 3 bytes based on chip sd */
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u64 bt_device = tegra_chip_uid() >> 24ull;
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btmacaddr[0] = (bt_device >> 1 & 0x0F) |
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(bt_device >> 5 & 0xF0);
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btmacaddr[1] = (bt_device >> 11 & 0x0F) |
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(bt_device >> 17 & 0xF0);
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btmacaddr[2] = (bt_device >> 23 & 0x0F) |
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(bt_device >> 29 & 0xF0);
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/* Set BT MAC address */
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fdt_find_and_setprop(blob, "/serial@70006200/bluetooth",
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"local-bd-address", btmacaddr, 6, 1);
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/* Remove TrustZone nodes */
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fdt_del_node_and_alias(blob, "/firmware");
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fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000");
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return 0;
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}
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#endif
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void nvidia_board_late_init(void)
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{
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char serialno_str[17];
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/* Set chip id as serialno */
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sprintf(serialno_str, "%016llx", tegra_chip_uid());
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env_set("serial#", serialno_str);
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env_set("platform", "Tegra 3 T30");
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}
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