mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-30 11:22:09 +00:00
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef _IMX8ULP_REGS_H_
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#define _IMX8ULP_REGS_H_
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#define ARCH_MXC
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#include <linux/bitops.h>
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#include <linux/sizes.h>
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#define PBRIDGE0_BASE 0x28000000
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#define CMC0_RBASE 0x28025000
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#define CMC1_BASE_ADDR 0x29240000
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#define SIM1_BASE_ADDR 0x29290000
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#define WDG3_RBASE 0x292a0000UL
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#define SIM_SEC_BASE_ADDR 0x2802B000
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#define CGC1_SOSCDIV_ADDR 0x292C0108
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#define CGC1_FRODIV_ADDR 0x292C0208
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#define CFG1_PLL2CSR_ADDR 0x292C0500
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#define CFG1_PLL2CFG_ADDR 0x292C0510
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#define PCC_XRDC_MGR_ADDR 0x292d00bc
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#define PCC3_RBASE 0x292d0000
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#define PCC4_RBASE 0x29800000
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#define PCC5_RBASE 0x2da70000
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#define IOMUXC_BASE_ADDR 0x298c0000
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#define LPUART4_RBASE 0x29390000
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#define LPUART5_RBASE 0x293a0000
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#define LPUART6_RBASE 0x29860000
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#define LPUART7_RBASE 0x29870000
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#define LPUART_BASE LPUART5_RBASE
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#define FSB_BASE_ADDR 0x27010000
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#define USBOTG0_RBASE 0x29900000
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#define USB_PHY0_BASE_ADDR 0x29910000
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#define USBOTG1_RBASE 0x29920000
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#define USB_PHY1_BASE_ADDR 0x29930000
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#define USB_BASE_ADDR USBOTG0_RBASE
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#define DDR_CTL_BASE_ADDR 0x2E060000
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#define DDR_PI_BASE_ADDR 0x2E062000
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#define DDR_PHY_BASE_ADDR 0x2E064000
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#define AVD_SIM_BASE_ADDR 0x2DA50000
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#define AVD_SIM_LPDDR_CTRL (AVD_SIM_BASE_ADDR + 0x14)
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#define AVD_SIM_LPDDR_CTRL2 (AVD_SIM_BASE_ADDR + 0x18)
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#define FEC_QUIRK_ENET_MAC
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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struct usbphy_regs {
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u32 usbphy_pwd; /* 0x000 */
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u32 usbphy_pwd_set; /* 0x004 */
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u32 usbphy_pwd_clr; /* 0x008 */
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u32 usbphy_pwd_tog; /* 0x00c */
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u32 usbphy_tx; /* 0x010 */
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u32 usbphy_tx_set; /* 0x014 */
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u32 usbphy_tx_clr; /* 0x018 */
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u32 usbphy_tx_tog; /* 0x01c */
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u32 usbphy_rx; /* 0x020 */
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u32 usbphy_rx_set; /* 0x024 */
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u32 usbphy_rx_clr; /* 0x028 */
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u32 usbphy_rx_tog; /* 0x02c */
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u32 usbphy_ctrl; /* 0x030 */
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u32 usbphy_ctrl_set; /* 0x034 */
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u32 usbphy_ctrl_clr; /* 0x038 */
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u32 usbphy_ctrl_tog; /* 0x03c */
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u32 usbphy_status; /* 0x040 */
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u32 reserved0[3];
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u32 usbphy_debug; /* 0x050 */
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u32 usbphy_debug_set; /* 0x054 */
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u32 usbphy_debug_clr; /* 0x058 */
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u32 usbphy_debug_tog; /* 0x05c */
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u32 usbphy_debug0_status; /* 0x060 */
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u32 reserved1[3];
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u32 usbphy_debug1; /* 0x070 */
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u32 usbphy_debug1_set; /* 0x074 */
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u32 usbphy_debug1_clr; /* 0x078 */
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u32 usbphy_debug1_tog; /* 0x07c */
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u32 usbphy_version; /* 0x080 */
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u32 reserved2[7];
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u32 usb1_pll_480_ctrl; /* 0x0a0 */
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u32 usb1_pll_480_ctrl_set; /* 0x0a4 */
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u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */
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u32 usb1_pll_480_ctrl_tog; /* 0x0ac */
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u32 reserved3[4];
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u32 usb1_vbus_detect; /* 0xc0 */
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u32 usb1_vbus_detect_set; /* 0xc4 */
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u32 usb1_vbus_detect_clr; /* 0xc8 */
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u32 usb1_vbus_detect_tog; /* 0xcc */
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u32 usb1_vbus_det_stat; /* 0xd0 */
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u32 reserved4[3];
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u32 usb1_chrg_detect; /* 0xe0 */
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u32 usb1_chrg_detect_set; /* 0xe4 */
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u32 usb1_chrg_detect_clr; /* 0xe8 */
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u32 usb1_chrg_detect_tog; /* 0xec */
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u32 usb1_chrg_det_stat; /* 0xf0 */
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u32 reserved5[3];
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u32 usbphy_anactrl; /* 0x100 */
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u32 usbphy_anactrl_set; /* 0x104 */
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u32 usbphy_anactrl_clr; /* 0x108 */
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u32 usbphy_anactrl_tog; /* 0x10c */
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u32 usb1_loopback; /* 0x110 */
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u32 usb1_loopback_set; /* 0x114 */
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u32 usb1_loopback_clr; /* 0x118 */
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u32 usb1_loopback_tog; /* 0x11c */
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u32 usb1_loopback_hsfscnt; /* 0x120 */
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u32 usb1_loopback_hsfscnt_set; /* 0x124 */
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u32 usb1_loopback_hsfscnt_clr; /* 0x128 */
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u32 usb1_loopback_hsfscnt_tog; /* 0x12c */
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u32 usphy_trim_override_en; /* 0x130 */
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u32 usphy_trim_override_en_set; /* 0x134 */
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u32 usphy_trim_override_en_clr; /* 0x138 */
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u32 usphy_trim_override_en_tog; /* 0x13c */
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u32 usb1_pfda_ctrl1; /* 0x140 */
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u32 usb1_pfda_ctrl1_set; /* 0x144 */
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u32 usb1_pfda_ctrl1_clr; /* 0x148 */
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u32 usb1_pfda_ctrl1_tog; /* 0x14c */
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};
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#endif
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#endif
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