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https://github.com/AsahiLinux/u-boot
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7964c30541
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephan Gerhold <stephan@gerhold.net> [trini: Add CONFIG_SDM845 around sdm845_data usage]
303 lines
7.7 KiB
C
303 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm pm8916 pmic gpio driver - part of Qualcomm PM8916 PMIC
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <power/pmic.h>
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#include <spmi/spmi.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/bitops.h>
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/* Register offset for each gpio */
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#define REG_OFFSET(x) ((x) * 0x100)
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/* Register maps */
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/* Type and subtype are shared for all pm8916 peripherals */
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#define REG_TYPE 0x4
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#define REG_SUBTYPE 0x5
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#define REG_STATUS 0x08
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#define REG_STATUS_VAL_MASK 0x1
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/* MODE_CTL */
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#define REG_CTL 0x40
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#define REG_CTL_MODE_MASK 0x70
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#define REG_CTL_MODE_INPUT 0x00
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#define REG_CTL_MODE_INOUT 0x20
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#define REG_CTL_MODE_OUTPUT 0x10
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#define REG_CTL_OUTPUT_MASK 0x0F
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#define REG_DIG_VIN_CTL 0x41
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#define REG_DIG_VIN_VIN0 0
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#define REG_DIG_PULL_CTL 0x42
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#define REG_DIG_PULL_NO_PU 0x5
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#define REG_DIG_OUT_CTL 0x45
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#define REG_DIG_OUT_CTL_CMOS (0x0 << 4)
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#define REG_DIG_OUT_CTL_DRIVE_L 0x1
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#define REG_EN_CTL 0x46
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#define REG_EN_CTL_ENABLE (1 << 7)
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struct pm8916_gpio_bank {
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uint32_t pid; /* Peripheral ID on SPMI bus */
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};
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static int pm8916_gpio_set_direction(struct udevice *dev, unsigned offset,
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bool input, int value)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
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int ret;
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/* Disable the GPIO */
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ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
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REG_EN_CTL_ENABLE, 0);
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if (ret < 0)
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return ret;
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/* Select the mode */
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if (input)
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ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
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REG_CTL_MODE_INPUT);
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else
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ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL,
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REG_CTL_MODE_INOUT | (value ? 1 : 0));
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if (ret < 0)
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return ret;
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/* Set the right pull (no pull) */
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ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
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REG_DIG_PULL_NO_PU);
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if (ret < 0)
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return ret;
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/* Configure output pin drivers if needed */
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if (!input) {
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/* Select the VIN - VIN0, pin is input so it doesn't matter */
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ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
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REG_DIG_VIN_VIN0);
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if (ret < 0)
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return ret;
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/* Set the right dig out control */
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ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
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REG_DIG_OUT_CTL_CMOS |
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REG_DIG_OUT_CTL_DRIVE_L);
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if (ret < 0)
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return ret;
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}
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/* Enable the GPIO */
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return pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL, 0,
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REG_EN_CTL_ENABLE);
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}
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static int pm8916_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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return pm8916_gpio_set_direction(dev, offset, true, 0);
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}
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static int pm8916_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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return pm8916_gpio_set_direction(dev, offset, false, value);
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}
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static int pm8916_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
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int reg;
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/* Set the output value of the gpio */
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reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);
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if (reg < 0)
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return reg;
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switch (reg & REG_CTL_MODE_MASK) {
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case REG_CTL_MODE_INPUT:
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return GPIOF_INPUT;
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case REG_CTL_MODE_INOUT: /* Fallthrough */
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case REG_CTL_MODE_OUTPUT:
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return GPIOF_OUTPUT;
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default:
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return GPIOF_UNKNOWN;
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}
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}
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static int pm8916_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
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int reg;
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reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);
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if (reg < 0)
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return reg;
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return !!(reg & REG_STATUS_VAL_MASK);
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}
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static int pm8916_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
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/* Set the output value of the gpio */
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return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
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REG_CTL_OUTPUT_MASK, !!value);
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}
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static const struct dm_gpio_ops pm8916_gpio_ops = {
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.direction_input = pm8916_gpio_direction_input,
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.direction_output = pm8916_gpio_direction_output,
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.get_value = pm8916_gpio_get_value,
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.set_value = pm8916_gpio_set_value,
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.get_function = pm8916_gpio_get_function,
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};
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static int pm8916_gpio_probe(struct udevice *dev)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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int reg;
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priv->pid = dev_read_addr(dev);
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if (priv->pid == FDT_ADDR_T_NONE)
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return log_msg_ret("bad address", -EINVAL);
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/* Do a sanity check */
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reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
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if (reg != 0x10)
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return log_msg_ret("bad type", -ENXIO);
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reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
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if (reg != 0x5 && reg != 0x1)
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return log_msg_ret("bad subtype", -ENXIO);
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return 0;
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}
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static int pm8916_gpio_of_to_plat(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 0);
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uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
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if (uc_priv->bank_name == NULL)
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uc_priv->bank_name = "pm8916";
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return 0;
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}
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static const struct udevice_id pm8916_gpio_ids[] = {
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{ .compatible = "qcom,pm8916-gpio" },
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{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
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{ .compatible = "qcom,pm8998-gpio" },
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{ }
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};
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U_BOOT_DRIVER(gpio_pm8916) = {
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.name = "gpio_pm8916",
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.id = UCLASS_GPIO,
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.of_match = pm8916_gpio_ids,
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.of_to_plat = pm8916_gpio_of_to_plat,
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.probe = pm8916_gpio_probe,
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.ops = &pm8916_gpio_ops,
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.priv_auto = sizeof(struct pm8916_gpio_bank),
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};
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/* Add pmic buttons as GPIO as well - there is no generic way for now */
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#define PON_INT_RT_STS 0x10
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#define KPDPWR_ON_INT_BIT 0
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#define RESIN_ON_INT_BIT 1
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static int pm8941_pwrkey_get_function(struct udevice *dev, unsigned offset)
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{
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return GPIOF_INPUT;
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}
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static int pm8941_pwrkey_get_value(struct udevice *dev, unsigned offset)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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int reg = pmic_reg_read(dev->parent, priv->pid + PON_INT_RT_STS);
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if (reg < 0)
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return 0;
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switch (offset) {
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case 0: /* Power button */
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return (reg & BIT(KPDPWR_ON_INT_BIT)) != 0;
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break;
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case 1: /* Reset button */
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default:
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return (reg & BIT(RESIN_ON_INT_BIT)) != 0;
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break;
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}
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}
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static const struct dm_gpio_ops pm8941_pwrkey_ops = {
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.get_value = pm8941_pwrkey_get_value,
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.get_function = pm8941_pwrkey_get_function,
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};
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static int pm8941_pwrkey_probe(struct udevice *dev)
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{
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struct pm8916_gpio_bank *priv = dev_get_priv(dev);
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int reg;
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priv->pid = dev_read_addr(dev);
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if (priv->pid == FDT_ADDR_T_NONE)
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return log_msg_ret("bad address", -EINVAL);
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/* Do a sanity check */
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reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
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if (reg != 0x1)
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return log_msg_ret("bad type", -ENXIO);
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reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
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if ((reg & 0x5) == 0)
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return log_msg_ret("bad subtype", -ENXIO);
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return 0;
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}
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static int pm8941_pwrkey_of_to_plat(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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uc_priv->gpio_count = 2;
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uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name");
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if (uc_priv->bank_name == NULL)
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uc_priv->bank_name = "pm8916_key";
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return 0;
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}
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static const struct udevice_id pm8941_pwrkey_ids[] = {
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{ .compatible = "qcom,pm8916-pwrkey" },
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{ .compatible = "qcom,pm8994-pwrkey" },
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{ .compatible = "qcom,pm8998-pwrkey" },
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{ }
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};
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U_BOOT_DRIVER(pwrkey_pm89xx) = {
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.name = "pwrkey_pm89xx",
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.id = UCLASS_GPIO,
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.of_match = pm8941_pwrkey_ids,
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.of_to_plat = pm8941_pwrkey_of_to_plat,
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.probe = pm8941_pwrkey_probe,
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.ops = &pm8941_pwrkey_ops,
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.priv_auto = sizeof(struct pm8916_gpio_bank),
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};
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