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https://github.com/AsahiLinux/u-boot
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6ee2c8ad58
The Linux devicetrees for Apple silicon devices are after review feedback switching from deleting unused PCIe ports to disabling them. Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/ Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
356 lines
9.6 KiB
C
356 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host bridge driver for Apple system-on-chips.
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*
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* The HW is ECAM compliant.
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*
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* Initialization requires enabling power and clocks, along with a
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* number of register pokes.
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*
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* Copyright (C) 2021 Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Copyright (C) 2021 Google LLC
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* Copyright (C) 2021 Corellium LLC
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* Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
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*
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* Author: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Author: Marc Zyngier <maz@kernel.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <mapmem.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#define CORE_RC_PHYIF_CTL 0x00024
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#define CORE_RC_PHYIF_CTL_RUN BIT(0)
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#define CORE_RC_PHYIF_STAT 0x00028
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#define CORE_RC_PHYIF_STAT_REFCLK BIT(4)
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#define CORE_RC_CTL 0x00050
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#define CORE_RC_CTL_RUN BIT(0)
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#define CORE_RC_STAT 0x00058
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#define CORE_RC_STAT_READY BIT(0)
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#define CORE_FABRIC_STAT 0x04000
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#define CORE_FABRIC_STAT_MASK 0x001F001F
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#define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
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#define CORE_LANE_CFG_REFCLK0REQ BIT(0)
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#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
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#define CORE_LANE_CFG_REFCLK0ACK BIT(2)
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#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
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#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
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#define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
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#define CORE_LANE_CTL_CFGACC BIT(15)
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#define PORT_LTSSMCTL 0x00080
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#define PORT_LTSSMCTL_START BIT(0)
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#define PORT_INTSTAT 0x00100
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#define PORT_INT_TUNNEL_ERR 31
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#define PORT_INT_CPL_TIMEOUT 23
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#define PORT_INT_RID2SID_MAPERR 22
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#define PORT_INT_CPL_ABORT 21
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#define PORT_INT_MSI_BAD_DATA 19
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#define PORT_INT_MSI_ERR 18
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#define PORT_INT_REQADDR_GT32 17
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#define PORT_INT_AF_TIMEOUT 15
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#define PORT_INT_LINK_DOWN 14
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#define PORT_INT_LINK_UP 12
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#define PORT_INT_LINK_BWMGMT 11
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#define PORT_INT_AER_MASK (15 << 4)
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#define PORT_INT_PORT_ERR 4
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#define PORT_INT_INTx(i) i
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#define PORT_INT_INTx_MASK 15
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#define PORT_INTMSK 0x00104
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#define PORT_INTMSKSET 0x00108
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#define PORT_INTMSKCLR 0x0010c
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#define PORT_MSICFG 0x00124
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#define PORT_MSICFG_EN BIT(0)
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#define PORT_MSICFG_L2MSINUM_SHIFT 4
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#define PORT_MSIBASE 0x00128
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#define PORT_MSIBASE_1_SHIFT 16
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#define PORT_MSIADDR 0x00168
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#define PORT_LINKSTS 0x00208
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#define PORT_LINKSTS_UP BIT(0)
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#define PORT_LINKSTS_BUSY BIT(2)
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#define PORT_LINKCMDSTS 0x00210
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#define PORT_OUTS_NPREQS 0x00284
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#define PORT_OUTS_NPREQS_REQ BIT(24)
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#define PORT_OUTS_NPREQS_CPL BIT(16)
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#define PORT_RXWR_FIFO 0x00288
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#define PORT_RXWR_FIFO_HDR GENMASK(15, 10)
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#define PORT_RXWR_FIFO_DATA GENMASK(9, 0)
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#define PORT_RXRD_FIFO 0x0028C
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#define PORT_RXRD_FIFO_REQ GENMASK(6, 0)
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#define PORT_OUTS_CPLS 0x00290
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#define PORT_OUTS_CPLS_SHRD GENMASK(14, 8)
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#define PORT_OUTS_CPLS_WAIT GENMASK(6, 0)
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#define PORT_APPCLK 0x00800
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#define PORT_APPCLK_EN BIT(0)
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#define PORT_APPCLK_CGDIS BIT(8)
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#define PORT_STATUS 0x00804
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#define PORT_STATUS_READY BIT(0)
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#define PORT_REFCLK 0x00810
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#define PORT_REFCLK_EN BIT(0)
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#define PORT_REFCLK_CGDIS BIT(8)
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#define PORT_PERST 0x00814
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#define PORT_PERST_OFF BIT(0)
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#define PORT_RID2SID(i16) (0x00828 + 4 * (i16))
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#define PORT_RID2SID_VALID BIT(31)
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#define PORT_RID2SID_SID_SHIFT 16
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#define PORT_RID2SID_BUS_SHIFT 8
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#define PORT_RID2SID_DEV_SHIFT 3
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#define PORT_RID2SID_FUNC_SHIFT 0
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#define PORT_OUTS_PREQS_HDR 0x00980
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#define PORT_OUTS_PREQS_HDR_MASK GENMASK(9, 0)
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#define PORT_OUTS_PREQS_DATA 0x00984
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#define PORT_OUTS_PREQS_DATA_MASK GENMASK(15, 0)
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#define PORT_TUNCTRL 0x00988
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#define PORT_TUNCTRL_PERST_ON BIT(0)
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#define PORT_TUNCTRL_PERST_ACK_REQ BIT(1)
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#define PORT_TUNSTAT 0x0098c
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#define PORT_TUNSTAT_PERST_ON BIT(0)
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#define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
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#define PORT_PREFMEM_ENABLE 0x00994
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struct apple_pcie_priv {
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struct udevice *dev;
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void __iomem *base;
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void __iomem *cfg_base;
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struct list_head ports;
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};
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struct apple_pcie_port {
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struct apple_pcie_priv *pcie;
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struct gpio_desc reset;
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ofnode np;
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void __iomem *base;
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struct list_head entry;
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int idx;
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};
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static void rmw_set(u32 set, void __iomem *addr)
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{
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writel_relaxed(readl_relaxed(addr) | set, addr);
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}
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static void rmw_clear(u32 clr, void __iomem *addr)
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{
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writel_relaxed(readl_relaxed(addr) & ~clr, addr);
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}
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static int apple_pcie_config_address(const struct udevice *bus,
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pci_dev_t bdf, uint offset,
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void **paddress)
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{
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struct apple_pcie_priv *pcie = dev_get_priv(bus);
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void *addr;
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addr = pcie->cfg_base;
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addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
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PCI_FUNC(bdf), offset);
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*paddress = addr;
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return 0;
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}
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static int apple_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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int ret;
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ret = pci_generic_mmap_read_config(bus, apple_pcie_config_address,
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bdf, offset, valuep, size);
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return ret;
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}
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static int apple_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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return pci_generic_mmap_write_config(bus, apple_pcie_config_address,
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bdf, offset, value, size);
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}
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static const struct dm_pci_ops apple_pcie_ops = {
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.read_config = apple_pcie_read_config,
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.write_config = apple_pcie_write_config,
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};
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static int apple_pcie_setup_refclk(struct apple_pcie_priv *pcie,
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struct apple_pcie_port *port)
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{
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u32 stat;
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int res;
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res = readl_poll_sleep_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat,
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stat & CORE_RC_PHYIF_STAT_REFCLK,
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100, 50000);
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if (res < 0)
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return res;
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rmw_set(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
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rmw_set(CORE_LANE_CFG_REFCLK0REQ, pcie->base + CORE_LANE_CFG(port->idx));
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res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
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stat, stat & CORE_LANE_CFG_REFCLK0ACK,
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100, 50000);
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if (res < 0)
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return res;
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rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base + CORE_LANE_CFG(port->idx));
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res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
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stat, stat & CORE_LANE_CFG_REFCLK1ACK,
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100, 50000);
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if (res < 0)
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return res;
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rmw_clear(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
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rmw_set(CORE_LANE_CFG_REFCLKEN, pcie->base + CORE_LANE_CFG(port->idx));
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rmw_set(PORT_REFCLK_EN, port->base + PORT_REFCLK);
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return 0;
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}
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static int apple_pcie_setup_port(struct apple_pcie_priv *pcie, ofnode np)
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{
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struct apple_pcie_port *port;
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struct gpio_desc reset;
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fdt_addr_t addr;
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u32 stat, idx;
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int ret;
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ret = gpio_request_by_name_nodev(np, "reset-gpios", 0, &reset, 0);
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if (ret)
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return ret;
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port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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ret = ofnode_read_u32_index(np, "reg", 0, &idx);
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if (ret)
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return ret;
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/* Use the first reg entry to work out the port index */
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port->idx = idx >> 11;
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port->pcie = pcie;
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port->reset = reset;
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port->np = np;
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addr = dev_read_addr_index(pcie->dev, port->idx + 2);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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port->base = map_sysmem(addr, 0);
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rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
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/* Assert PERST# before setting up the clock */
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dm_gpio_set_value(&reset, 1);
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ret = apple_pcie_setup_refclk(pcie, port);
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if (ret < 0)
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return ret;
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/* The minimal Tperst-clk value is 100us (PCIe CEM r5.0, 2.9.2) */
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udelay(100);
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/* Deassert PERST# */
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rmw_set(PORT_PERST_OFF, port->base + PORT_PERST);
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dm_gpio_set_value(&reset, 0);
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/* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
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udelay(100 * 1000);
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ret = readl_poll_sleep_timeout(port->base + PORT_STATUS, stat,
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stat & PORT_STATUS_READY, 100, 250000);
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if (ret < 0) {
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dev_err(pcie->dev, "port %d ready wait timeout\n", port->idx);
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return ret;
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}
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rmw_clear(PORT_REFCLK_CGDIS, port->base + PORT_REFCLK);
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rmw_clear(PORT_APPCLK_CGDIS, port->base + PORT_APPCLK);
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list_add_tail(&port->entry, &pcie->ports);
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writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
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/*
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* Deliberately ignore the link not coming up as connected
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* devices (e.g. the WiFi controller) may not be powerd up.
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*/
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readl_poll_sleep_timeout(port->base + PORT_LINKSTS, stat,
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(stat & PORT_LINKSTS_UP), 100, 100000);
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return 0;
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}
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static int apple_pcie_probe(struct udevice *dev)
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{
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struct apple_pcie_priv *pcie = dev_get_priv(dev);
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fdt_addr_t addr;
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ofnode of_port;
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int i, ret;
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pcie->dev = dev;
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addr = dev_read_addr_index(dev, 0);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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pcie->cfg_base = map_sysmem(addr, 0);
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addr = dev_read_addr_index(dev, 1);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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pcie->base = map_sysmem(addr, 0);
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INIT_LIST_HEAD(&pcie->ports);
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for (of_port = ofnode_first_subnode(dev_ofnode(dev));
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ofnode_valid(of_port);
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of_port = ofnode_next_subnode(of_port)) {
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if (!ofnode_is_enabled(of_port))
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continue;
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ret = apple_pcie_setup_port(pcie, of_port);
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if (ret) {
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dev_err(pcie->dev, "Port %d setup fail: %d\n", i, ret);
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return ret;
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}
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}
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return 0;
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}
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static int apple_pcie_remove(struct udevice *dev)
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{
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struct apple_pcie_priv *pcie = dev_get_priv(dev);
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struct apple_pcie_port *port, *tmp;
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list_for_each_entry_safe(port, tmp, &pcie->ports, entry) {
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gpio_free_list_nodev(&port->reset, 1);
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free(port);
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}
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return 0;
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}
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static const struct udevice_id apple_pcie_of_match[] = {
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{ .compatible = "apple,pcie" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(apple_pcie) = {
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.name = "apple_pcie",
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.id = UCLASS_PCI,
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.of_match = apple_pcie_of_match,
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.probe = apple_pcie_probe,
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.remove = apple_pcie_remove,
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.priv_auto = sizeof(struct apple_pcie_priv),
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.ops = &apple_pcie_ops,
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};
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