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https://github.com/AsahiLinux/u-boot
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53b40e8d54
The use of ARMv8.3 pointer authentication (PAuth) is governed by fields in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset value of these fields is 'architecturally unknown' so we must ensure that the fields are enabled (to disable the traps) if we are entering the kernel at EL1. The APK field disables PAuth instruction traps and the API field disables PAuth register traps Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer authentication is supported by the hardware. The runtime checks require a second temporary register, so add this to the EL1 transition macro signature and update 2 call sites. Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
118 lines
2.8 KiB
ArmAsm
118 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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* Copyright 2019 NXP
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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.align 3
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.global secondary_boot_addr
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secondary_boot_addr:
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.quad __secondary_boot_func
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.global secondary_boot_code_start
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secondary_boot_code_start:
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.quad __secondary_boot_code_start
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.global secondary_boot_code_size
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secondary_boot_code_size:
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.quad __secondary_boot_code_end - __secondary_boot_code_start
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 3
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/* Secondary Boot Code starts here */
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__secondary_boot_code_start:
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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__secondary_boot_func:
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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* table (each elem is padded to 64 bytes)
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*/
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lsl x1, x10, #6
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adr x0, __spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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adr x0, __real_cntfrq
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ldr x0, [x0]
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msr cntfrq_el0, x0 /* set with real frequency */
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str x9, [x11, #16] /* LPID */
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mov x4, #1
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str x4, [x11, #8] /* STATUS */
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dsb sy
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1:
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wfe
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ldr x4, [x11]
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cbz x4, 1b
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mrs x1, sctlr_el2
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tbz x1, #25, 2f
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rev x4, x4 /* BE to LE conversion */
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2:
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ldr x6, =ES_TO_AARCH64
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x5, 3f
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switch_el x7, 0f, _dead_loop, _dead_loop
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0: armv8_switch_to_el2_m x5, x6, x7
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#endif
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3:
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ldr x7, [x11, #24] /* ARCH_COMP */
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cbz x7, 4f
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ldr x6, =ES_TO_AARCH32
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4:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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switch_el x7, _dead_loop, 0f, _dead_loop
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0: armv8_switch_to_el1_m x4, x6, x7, x9
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#else
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switch_el x7, 0f, _dead_loop, _dead_loop
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0: armv8_switch_to_el2_m x4, x6, x7
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#endif
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_dead_loop:
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wfe
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b _dead_loop
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/* Ensure that the literals used by the secondary boot code are
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* assembled within it (this is required so that we can protect
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* this area with a single memreserve region
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*/
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.ltorg
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/* 64 bit alignment for elements accessed as data */
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.align 3
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.global __real_cntfrq
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__real_cntfrq:
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.quad COUNTER_FREQUENCY
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/* Secondary Boot Code ends here */
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__secondary_boot_code_end:
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