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35fe948e3b
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
175 lines
5.2 KiB
Makefile
175 lines
5.2 KiB
Makefile
#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2002,2003 Motorola Inc.
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# Xianghua Xiao,X.Xiao@motorola.com
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).o
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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START = start.o resetvec.o
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ifdef MINIMAL
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COBJS-y += cpu_init_early.o tlb.o spl_minimal.o
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else
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SOBJS-$(CONFIG_MP) += release.o
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SOBJS = $(SOBJS-y)
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COBJS-$(CONFIG_CMD_ERRATA) += cmd_errata.o
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COBJS-$(CONFIG_CPM2) += commproc.o
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# supports ddr1
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COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
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COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
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COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
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COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
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# supports ddr1/2
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COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
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COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
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COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
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# supports ddr1/2/3
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COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
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COBJS-$(CONFIG_P1010) += ddr-gen3.o
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COBJS-$(CONFIG_P1011) += ddr-gen3.o
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COBJS-$(CONFIG_P1012) += ddr-gen3.o
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COBJS-$(CONFIG_P1013) += ddr-gen3.o
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COBJS-$(CONFIG_P1014) += ddr-gen3.o
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COBJS-$(CONFIG_P1020) += ddr-gen3.o
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COBJS-$(CONFIG_P1021) += ddr-gen3.o
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COBJS-$(CONFIG_P1022) += ddr-gen3.o
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COBJS-$(CONFIG_P1024) += ddr-gen3.o
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COBJS-$(CONFIG_P1025) += ddr-gen3.o
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COBJS-$(CONFIG_P2010) += ddr-gen3.o
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COBJS-$(CONFIG_P2020) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P2041) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
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COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
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COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
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COBJS-$(CONFIG_BSC9132) += ddr-gen3.o
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COBJS-$(CONFIG_CPM2) += ether_fcc.o
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COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
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COBJS-$(CONFIG_FSL_CORENET) += liodn.o
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COBJS-$(CONFIG_MP) += mp.o
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COBJS-$(CONFIG_PCI) += pci.o
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COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
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# various SoC specific assignments
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COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
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COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
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COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
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COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
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COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
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COBJS-$(CONFIG_QE) += qe_io.o
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COBJS-$(CONFIG_CPM2) += serial_scc.o
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COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
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COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
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# SoC specific SERDES support
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COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
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COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
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COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
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COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
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COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
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COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
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COBJS-$(CONFIG_P1010) += p1010_serdes.o
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COBJS-$(CONFIG_P1011) += p1021_serdes.o
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COBJS-$(CONFIG_P1012) += p1021_serdes.o
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COBJS-$(CONFIG_P1013) += p1022_serdes.o
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COBJS-$(CONFIG_P1014) += p1010_serdes.o
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COBJS-$(CONFIG_P1017) += p1023_serdes.o
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COBJS-$(CONFIG_P1020) += p1021_serdes.o
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COBJS-$(CONFIG_P1021) += p1021_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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COBJS-$(CONFIG_P1023) += p1023_serdes.o
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COBJS-$(CONFIG_P1024) += p1021_serdes.o
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COBJS-$(CONFIG_P1025) += p1021_serdes.o
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COBJS-$(CONFIG_P2010) += p2020_serdes.o
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COBJS-$(CONFIG_P2020) += p2020_serdes.o
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COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
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COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
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COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
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COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
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COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
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COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
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COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
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COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
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COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
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COBJS-y += cpu.o
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COBJS-y += cpu_init.o
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COBJS-y += cpu_init_early.o
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COBJS-y += interrupts.o
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COBJS-y += speed.o
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COBJS-y += tlb.o
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COBJS-y += traps.o
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# Stub implementations of cache management functions for USB
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COBJS-y += cache.o
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endif # not minimal
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COBJS = $(COBJS-y)
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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START := $(addprefix $(obj),$(START))
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all: $(obj).depend $(START) $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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