mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
113 lines
2.7 KiB
C
113 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <console.h>
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#include <env.h>
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#include <env_internal.h>
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#include <init.h>
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#include <ns16550.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <nand.h>
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#include <i2c.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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#include <asm/global_data.h>
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#include "../common/spl.h"
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L2_SIZE;
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}
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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console_init_f();
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/* Clock configuration to access CPLD using IFC(GPCM) */
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setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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#ifdef CONFIG_TARGET_P1010RDB_PB
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
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#endif
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = get_board_sys_clk() * plat_ratio;
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ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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#ifdef CONFIG_SPL_MMC_BOOT
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puts("\nSD boot...\n");
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#elif defined(CONFIG_SPL_SPI_BOOT)
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puts("\nSPI Flash boot...\n");
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#endif
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *)CONFIG_SPL_GD_ADDR;
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struct bd_info *bd;
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memset(gd, 0, sizeof(gd_t));
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bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
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memset(bd, 0, sizeof(struct bd_info));
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gd->bd = bd;
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arch_cpu_init();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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gd->flags |= GD_FLG_FULL_MALLOC_INIT;
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#ifndef CONFIG_SPL_NAND_BOOT
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env_init();
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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#endif
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/* relocate environment function pointers etc. */
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)SPL_ENV_ADDR);
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gd->env_addr = (ulong)(SPL_ENV_ADDR);
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gd->env_valid = ENV_VALID;
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#else
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env_relocate();
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#endif
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i2c_init_all();
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dram_init();
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#ifdef CONFIG_SPL_NAND_BOOT
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puts("\nTertiary program loader running in sram...");
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#else
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puts("\nSecond program loader running in sram...");
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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fsl_spi_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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