mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 07:57:21 +00:00
983e37007d
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
90 lines
1.8 KiB
ArmAsm
90 lines
1.8 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/arch/omap.h>
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#include <asm/omap_common.h>
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#include <asm/arch/spl.h>
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#include <linux/linkage.h>
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.arch_extension sec
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#ifdef CONFIG_SPL
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ENTRY(save_boot_params)
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ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
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str r0, [r1]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE)
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ENTRY(switch_to_hypervisor)
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/*
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* Switch to hypervisor mode
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*/
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adr r0, save_sp
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str sp, [r0]
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adr r1, restore_from_hyp
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ldr r0, =0x102
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b omap_smc1
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restore_from_hyp:
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adr r0, save_sp
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ldr sp, [r0]
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MRC p15, 4, R0, c1, c0, 0
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ldr r1, =0X1004 @Set cache enable bits for hypervisor mode
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orr r0, r0, r1
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MCR p15, 4, R0, c1, c0, 0
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b switch_to_hypervisor_ret
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save_sp:
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.word 0x0
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ENDPROC(switch_to_hypervisor)
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#endif
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#endif
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ENTRY(omap_smc1)
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push {r4-r12, lr} @ save registers - ROM code may pollute
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@ our registers
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mov r12, r0 @ Service
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mov r0, r1 @ Argument
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dsb
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dmb
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smc 0 @ SMC #0 to enter monitor mode
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@ call ROM Code API for the service requested
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pop {r4-r12, pc}
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ENDPROC(omap_smc1)
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ENTRY(omap_smc_sec)
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push {r4-r12, lr} @ save registers - ROM code may pollute
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@ our registers
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mov r6, #0xFF @ Indicate new Task call
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mov r12, #0x00 @ Secure Service ID in R12
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dsb
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dmb
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smc 0 @ SMC #0 to enter monitor mode
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b omap_smc_sec_end @ exit at end of the service execution
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nop
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@ In case of IRQ happening in Secure, then ARM will branch here.
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@ At that moment, IRQ will be pending and ARM will jump to Non Secure
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@ IRQ handler
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mov r12, #0xFE
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dsb
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dmb
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smc 0 @ SMC #0 to enter monitor mode
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omap_smc_sec_end:
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pop {r4-r12, pc}
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ENDPROC(omap_smc_sec)
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