mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
0914011310
We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
417 lines
9.3 KiB
C
417 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <fdt_support.h>
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#include <hang.h>
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#include <i2c.h>
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#include <asm/cache.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_FSL_LS_PPA
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#include <asm/arch/ppa.h>
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#endif
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#include <asm/arch/mmu.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fsl_esdhc.h>
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#include <env_internal.h>
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#include <fsl_mmdc.h>
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#include <netdev.h>
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#include <fsl_sec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define BOOT_FROM_UPPER_BANK 0x2
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#define BOOT_FROM_LOWER_BANK 0x1
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int checkboard(void)
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{
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#ifdef CONFIG_TARGET_LS1012ARDB
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u8 in1;
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int ret, bus_num = 0;
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puts("Board: LS1012ARDB ");
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/* Initialize i2c early for Serial flash bank information */
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#if defined(CONFIG_DM_I2C)
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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bus_num);
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return -ENXIO;
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}
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ret = dm_i2c_read(dev, I2C_MUX_IO_1, &in1, 1);
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#else /* Non DM I2C support - will be removed */
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i2c_set_bus_num(bus_num);
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ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &in1, 1);
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#endif
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if (ret < 0) {
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printf("Error reading i2c boot information!\n");
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return 0; /* Don't want to hang() on this error */
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}
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puts("Version");
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switch (in1 & SW_REV_MASK) {
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case SW_REV_A:
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puts(": RevA");
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break;
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case SW_REV_B:
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puts(": RevB");
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break;
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case SW_REV_C:
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puts(": RevC");
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break;
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case SW_REV_C1:
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puts(": RevC1");
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break;
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case SW_REV_C2:
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puts(": RevC2");
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break;
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case SW_REV_D:
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puts(": RevD");
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break;
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case SW_REV_E:
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puts(": RevE");
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break;
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default:
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puts(": unknown");
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break;
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}
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printf(", boot from QSPI");
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if ((in1 & SW_BOOT_MASK) == SW_BOOT_EMU)
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puts(": emu\n");
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else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK1)
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puts(": bank1\n");
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else if ((in1 & SW_BOOT_MASK) == SW_BOOT_BANK2)
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puts(": bank2\n");
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else
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puts("unknown\n");
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#else
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puts("Board: LS1012A2G5RDB ");
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#endif
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return 0;
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}
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#ifdef CONFIG_TFABOOT
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int dram_init(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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#else
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int dram_init(void)
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{
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#ifndef CONFIG_TFABOOT
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static const struct fsl_mmdc_info mparam = {
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0x05180000, /* mdctl */
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0x00030035, /* mdpdc */
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0x12554000, /* mdotc */
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0xbabf7954, /* mdcfg0 */
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0xdb328f64, /* mdcfg1 */
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0x01ff00db, /* mdcfg2 */
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0x00001680, /* mdmisc */
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0x0f3c8000, /* mdref */
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0x00002000, /* mdrwd */
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0x00bf1023, /* mdor */
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0x0000003f, /* mdasp */
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0x0000022a, /* mpodtctrl */
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0xa1390003, /* mpzqhwctrl */
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};
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mmdc_init(&mparam);
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#endif
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
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/* This will break-before-make MMU for DDR */
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update_early_mmu_table();
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#endif
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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if (current_el() == 3)
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_TARGET_LS1012ARDB
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int esdhc_status_fixup(void *blob, const char *compat)
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{
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char esdhc1_path[] = "/soc/esdhc@1580000";
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bool sdhc2_en = false;
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u8 mux_sdhc2;
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u8 io = 0;
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int ret, bus_num = 0;
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#if defined(CONFIG_DM_I2C)
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_IO_ADDR,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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bus_num);
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return -ENXIO;
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}
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ret = dm_i2c_read(dev, I2C_MUX_IO_1, &io, 1);
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#else
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i2c_set_bus_num(bus_num);
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/* IO1[7:3] is the field of board revision info. */
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ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_1, 1, &io, 1);
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#endif
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if (ret < 0) {
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printf("Error reading i2c boot information!\n");
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return 0;
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}
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/* hwconfig method is used for RevD and later versions. */
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if ((io & SW_REV_MASK) <= SW_REV_D) {
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#ifdef CONFIG_HWCONFIG
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if (hwconfig("esdhc1"))
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sdhc2_en = true;
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#endif
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} else {
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/*
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* The I2C IO-expander for mux select is used to control
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* the muxing of various onboard interfaces.
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*
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* IO0[3:2] indicates SDHC2 interface demultiplexer
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* select lines.
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* 00 - SDIO wifi
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* 01 - GPIO (to Arduino)
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* 10 - eMMC Memory
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* 11 - SPI
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*/
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#if defined(CONFIG_DM_I2C)
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ret = dm_i2c_read(dev, I2C_MUX_IO_0, &io, 1);
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#else
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ret = i2c_read(I2C_MUX_IO_ADDR, I2C_MUX_IO_0, 1, &io, 1);
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#endif
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if (ret < 0) {
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printf("Error reading i2c boot information!\n");
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return 0;
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}
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mux_sdhc2 = (io & 0x0c) >> 2;
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/* Enable SDHC2 only when use SDIO wifi and eMMC */
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if (mux_sdhc2 == 2 || mux_sdhc2 == 0)
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sdhc2_en = true;
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}
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if (sdhc2_en)
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do_fixup_by_path(blob, esdhc1_path, "status", "okay",
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sizeof("okay"), 1);
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else
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do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
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sizeof("disabled"), 1);
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return 0;
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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arch_fixup_fdt(blob);
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ft_cpu_setup(blob, bd);
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return 0;
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}
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static int switch_to_bank1(void)
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{
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u8 data = 0xf4, chip_addr = 0x24, offset_addr = 0x03;
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int ret, bus_num = 0;
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#if defined(CONFIG_DM_I2C)
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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bus_num);
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return -ENXIO;
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}
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/*
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* --------------------------------------------------------------------
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* |bus |I2C address| Device | Notes |
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* --------------------------------------------------------------------
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* |I2C1|0x24, 0x25,| IO expander (CFG,| Provides 16bits of General |
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* | |0x26 | RESET, and INT/ | Purpose parallel Input/Output|
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* | | | KW41GPIO) - NXP | (GPIO) expansion for the |
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* | | | PCAL9555AHF | I2C bus |
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* ----- --------------------------------------------------------------
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* - mount three IO expander(PCAL9555AHF) on I2C1
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*
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* PCAL9555A device address
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* slave address
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* --------------------------------------
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* | 0 | 1 | 0 | 0 | A2 | A1 | A0 | R/W |
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* --------------------------------------
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* | fixed | hardware selectable|
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*
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* Output port 1(Pinter register bits = 0x03)
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*
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* P1_[7~0] = 0xf4
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* P1_0 <---> CFG_MUX_QSPI_S0
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* P1_1 <---> CFG_MUX_QSPI_S1
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* CFG_MUX_QSPI_S[1:0] = 0b00
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*
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* QSPI chip-select demultiplexer select
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* ---------------------------------------------------------------------
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* CFG_MUX_QSPI_S1|CFG_MUX_QSPI_S0| Values
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* ---------------------------------------------------------------------
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* 0 | 0 |CS routed to SPI memory bank1(default)
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* ---------------------------------------------------------------------
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* 0 | 1 |CS routed to SPI memory bank2
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* ---------------------------------------------------------------------
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*
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*/
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ret = dm_i2c_write(dev, offset_addr, &data, 1);
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#else /* Non DM I2C support - will be removed */
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i2c_set_bus_num(bus_num);
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ret = i2c_write(chip_addr, offset_addr, 1, &data, 1);
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#endif
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if (ret) {
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printf("i2c write error to chip : %u, addr : %u, data : %u\n",
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chip_addr, offset_addr, data);
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}
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return ret;
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}
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static int switch_to_bank2(void)
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{
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u8 data[2] = {0xfc, 0xf5}, offset_addr[2] = {0x7, 0x3};
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u8 chip_addr = 0x24;
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int ret, i, bus_num = 0;
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#if defined(CONFIG_DM_I2C)
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(bus_num, chip_addr,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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bus_num);
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return -ENXIO;
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}
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#else /* Non DM I2C support - will be removed */
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i2c_set_bus_num(bus_num);
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#endif
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/*
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* 1th step: config port 1
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* - the port 1 pin is enabled as an output
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* 2th step: output port 1
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* - P1_[7:0] output 0xf5,
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* then CFG_MUX_QSPI_S[1:0] equal to 0b01,
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* CS routed to SPI memory bank2
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*/
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for (i = 0; i < sizeof(data); i++) {
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#if defined(CONFIG_DM_I2C)
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ret = dm_i2c_write(dev, offset_addr[i], &data[i], 1);
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#else /* Non DM I2C support - will be removed */
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ret = i2c_write(chip_addr, offset_addr[i], 1, &data[i], 1);
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#endif
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if (ret) {
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printf("i2c write error to chip : %u, addr : %u, data : %u\n",
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chip_addr, offset_addr[i], data[i]);
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goto err;
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}
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}
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err:
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return ret;
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}
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static int convert_flash_bank(int bank)
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{
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int ret = 0;
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switch (bank) {
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case BOOT_FROM_UPPER_BANK:
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ret = switch_to_bank2();
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break;
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case BOOT_FROM_LOWER_BANK:
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ret = switch_to_bank1();
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break;
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default:
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ret = CMD_RET_USAGE;
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break;
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};
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return ret;
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}
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static int flash_bank_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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if (argc != 2)
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return CMD_RET_USAGE;
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if (strcmp(argv[1], "1") == 0)
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convert_flash_bank(BOOT_FROM_LOWER_BANK);
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else if (strcmp(argv[1], "2") == 0)
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convert_flash_bank(BOOT_FROM_UPPER_BANK);
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else
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return CMD_RET_USAGE;
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return 0;
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}
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U_BOOT_CMD(
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boot_bank, 2, 0, flash_bank_cmd,
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"Flash bank Selection Control",
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"bank[1-lower bank/2-upper bank] (e.g. boot_bank 1)"
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);
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